Method and apparatus for error injection techniques

• US 5,875,195 A
• Filed: 03/31/1997
• Issued: 02/23/1999
• Est. Priority Date: 03/31/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dixon, Robert Christopher
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/829,087
• Time in Patent Office: 694 Days
• Field of Search: 371/21.2, 371/21.3, 371/21.6, 365/201, 395/182.03, 395/182.04
• US Class Current: 714/719
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

A process and implementing computer system in which a power-on self-test (POST) routine initially clears 203 a mask register 111 which is effective to mask or block data from being written to addresses in a synchronous DRAM or SDRAM 107. After disabling interrupts and caches, the tested SDRAM memory 107 is cleared to all "0"s. Sequential data byte lanes are tested by writing bits in a predetermined pattern to inject errors at predetermined bytes in SDRAM, setting selected mask register bits and then writing all "0"s to the predetermined addresses. The tested memory locations are read and compared with the predetermined pattern for errors. Detected errors are noted by recordation and the memory locations are cleared as the method recycles until all of the data byte lanes have been tested and the results recorded.

Claims

1. A method for testing a memory, said method comprising:

clearing said memory;

writing a first test pattern of test signals to said memory;

blocking predetermined data paths to said memory;

writing a second test pattern of test signals to said memory;

unblocking the data paths to said memory; and

reading predetermined memory locations in said memory to provide a readout pattern.

2. The method as set forth in claim 1 and further including:

comparing said readout pattern with said first test pattern of test signals.

3. The method as set forth in claim 2 wherein after said comparing, said method further includes providing an output signal representative of variances between said readout pattern and said first test pattern of test signals.

4. The method as set forth in claim 3 wherein said output signal is representative of a number of bit positions containing variances between said readout pattern and said first test pattern of test signals.

5. The method as set forth in claim 3 and further including:

storing said output signal in a storage device.

6. The method as set forth in claim 3 and further including:

transmitting said output signal to a storage device; and

storing said output signal in said storage device.

7. The method as set forth in claim 1 and further including:

repeating said method for separate groups of data paths until all of said data paths have been tested.

8. The method as set forth in claim 7 and further including, after said reading:

clearing said memory after each cycle of testing each group of said separate groups of said data paths.

9. The method as set forth in claim 5 and further including:

repeating said method for separate groups of data paths until all of said data paths have been tested.

10. The method as set forth in claim 9 and further including, after said reading:

clearing said memory after each cycle of testing each group of said separate groups of said data paths.

11. The method as set forth in claim 1 wherein said second test pattern comprises all logic "0" level test signals.

12. The method as set forth in claim 1 and further including:

executing said method at predetermined times.

13. The method as set forth in claim 12 wherein said memory is within an information processing system, said method further including:

executing said method at each power-on of said information processing system.

14. The method as set forth in claim 13 wherein said method is executed at predetermined times following said power-on time.

15. An information processing system comprising:

a processor device;

a memory device;

a memory controller connected between said processor and said memory device;

a data path controller connected between said processor and said memory device; and

a masking device connected to said memory device, said masking device being selectively responsive to masking signals applied thereto for masking selected data paths between said data path controller and said memory device.

16. The information processing system as set forth in claim 15 wherein said masking device is implemented separately from said memory controller.

17. The information processing system as set forth in claim 15 wherein said masking device is implemented within said memory controller device.

18. The information processing system as set forth in claim 15 wherein said masking device is comprised of:

a masking register wherein each bit position of said masking register corresponds to a predetermined data byte lane of data paths to said memory device;

an OR gate connecting said masking register to said memory device; and

a select circuit connected to said masking register, said select circuit being effective to enable a selection of said masking register during a memory test procedure, said select circuit being further effective to disable said masking register at times when said memory test procedure is not executing.

19. A storage medium including machine readable indicia, said storage medium being selectively coupled to a reading device, said reading device being coupled to processing circuitry, said reading device being selectively operable to read said machine readable indicia and provide program signals representative thereof, said program signals being effective to cause said processing circuitry to test a memory by performing the steps of:

clearing said memory;

writing a first test pattern of test signals to said memory;

blocking predetermined data paths to said memory;

writing a second test pattern of test signals to said memory;

unblocking the data paths to said memory; and

reading predetermined memory locations in said memory to provide an readout pattern.

20. The storage medium as set forth in claim 19 wherein said program signals are further effective, when applied to said processing circuitry, for:

comparing said readout pattern with said first test pattern of test signals.

21. The storage medium as set forth in claim 20 wherein after said comparing, said program signals are further effective, when applied to said processing circuitry, for providing an output signal representative of variances between said readout pattern and said first test pattern of test signals.

22. The storage medium as set forth in claim 21 wherein said output signal is representative of a number of bit positions containing variances between said readout pattern and said first test pattern of test signals.

23. The storage medium as set forth in claim 21 wherein said program signals are further effective, when applied to said processing circuitry, for:

storing said output signal in a storage device.

24. The storage medium as set forth in claim 21 wherein said program signals are further effective, when applied to said processing circuitry, for:

transmitting said output signal to a storage device; and

storing said output signal in said storage device.

25. The storage medium as set forth in claim 19 wherein said program signals are further effective, when applied to said processing circuitry, for:

repeating said steps for separate groups of data paths until all of said data paths have been tested.

26. The storage medium as set forth in claim 25 wherein, after said reading, said program signals are further effective, when applied to said processing circuitry, for:

clearing said memory after each cycle of testing each group of said separate groups of said data paths.

27. The storage medium as set forth in claim 23 wherein said program signals are further effective, when applied to said processing circuitry, for:

repeating said steps for separate groups of data paths until all of said data paths have been tested.

28. The storage medium as set forth in claim 27, and, after said reading, said program signals are further effective, when applied to said processing circuitry, for:

clearing said memory after each cycle of testing each group of said separate groups of said data paths.

29. The storage medium as set forth in claim 19 wherein said second test pattern comprises all logic "0" level test signals.

30. The storage medium as set forth in claim 19 wherein said program signals are further effective, when applied to said processing circuitry, for:

causing an execution of said steps at predetermined times.

31. The storage medium as set forth in claim 30 wherein said memory is within an information processing system, wherein said program signals are further effective, when applied to said processing circuitry, for causing an execution of said steps at each power-on of said information processing system.

32. The storage medium as set forth in claim 31 wherein said program signals are further effective, when applied to said processing circuitry, for causing an execution of said steps at predetermined times following said power-on time.