Processor using implicit register addressing

• US 5,875,323 A
• Filed: 10/25/1995
• Issued: 02/23/1999
• Est. Priority Date: 12/13/1994
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Machida, Hirohisa
• Primary Examiner(s): Ellis, Richard L.
• Assistant Examiner(s): Winder, Patrice L.
• Application Number:
  US08/547,798
• Time in Patent Office: 1,217 Days
• Field of Search: 395/562, 395/568, 395/567, 395/800, 395/571, 395/570, 395/500, 395/378, 395/386, 395/388, 395/564, 395/565, 395/566, 395/561, 395/800.23, 395/384, 364/247, 364/247.8
• US Class Current: 712/221
• CPC Class Codes: G06F 9/30163 with implied specifier, e.g. top of stack
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

To obtain a high performance computer decreased in the number of commands to be executed. A control circuit receives a command (CMD), and outputs a special command signal which becomes "H" when the command (CMD) instructs "push" command, to a register file. The register file, when the special command signal is "H", outputs the stored data value of register as register data regardless of the values of read register address signals, and and outputs the stored data value of register as register data. An ALU adds the register data and control data, and outputs the ALU operation result to the register file. An address adder adds the register data and control data, and outputs the address addition result to an external memory.

Claims

1. A computer comprising:

a data read section including plural registers for receiving a command obtained from outside, and outputting stored data of said plural registers selectively as read data based on said command, said command containing a special command implicitly referencing registers for reading out stored data; and

a data operation section for operating according to said read data to output an operation result;

wherein said data read section specifies two registers out of said plural registers as first and second specific registers when said command is said special command, and for outputting first stored data which is stored data of said first specific register and second stored data which is stored data of said second specific register as said read data.

2. The computer of claim 1, wherein said data read section comprises:

control means for outputting a read address signal based on said command, and asserting a special command signal when said command is said special command; and

a register group including said plural registers, for receiving said read address signal, and outputting stored data of said plural registers selectively as said read data based on said read address signal, wherein said register group further receives said special command signal, and outputs said first and second stored data of said first and second specific registers as said read data regardless of said read address signal when said special command is asserted.

3. The computer of claim 1,

wherein said special command is specified by a type of command, a first number, and a second number;

said data read section further outputs said first number and second number as said read data when said command is said special command;

said data operation section comprising;

first operation means for operating according to said first stored data and said first number to output a first operation result; and

second operation means for operating according to said second stored data and said second number to output a second operation result.

4. The computer of claim 3,

wherein said data read section writes said first operation result into said first specific register when said command is said special command;

and

wherein said second operation result is specified as a write address of an external memory, and said second stored data is specified as write data to be written into said write address of said external memory.

5. A computer comprising:

a data read section including plural registers for outputting stored data of said plural registers selectively as read data based on a command obtained from outside, said command containing a special command implicitly referencing a reference register for reading out stored data; and

a data operation unit for operating according to said read data and outputting an operation result;

wherein said data read section specifies said reference register out of said plural registers when said command is said special command, and for outputting reference stored data which is stored data in said reference register as said read data; and

wherein said data operation section comprises data comparative means for comparing said reference stored data with comparative data to output a comparative result signal.

8. The computer of claim 5,

wherein said special command further implicitly references an addition register;

wherein said controller further specifies said addition register other than said reference register, and selected from said plural registers, when said command is said special command, and further outputs addition stored data which is stored data in said addition register as said read data; and

wherein said comparative data is generated based on said addition stored data.

9. The computer of claim 8,

wherein said data read section comprises:

control means for outputting a read address signal based on said command, and asserting a special command signal when said command is a special command; and

a register group including said plural registers, for receiving said read address signal, and outputting stored data of said plural registers selectively as said read data based on said read address signal, wherein said register group further receives said special command signal, and outputs said reference stored data of said reference register and said addition stored data of said addition register as said read data regardless of said read address signal when said special command is asserted.

10. The computer of claim 8,

wherein said special command specifies a predetermined number for additions;

said data read section further outputs for outputting said predetermined number for additions as said read data when said command is said special command; and

an adder for generating said comparative data by adding said predetermined number for additions to said addition stored data.

11. The computer of claim 10, wherein said data read section comprises outputs for writing said comparative data into said addition register when said command is said special command.

12. The computer of claim 8, wherein said data read section comprises:

control means for outputting a read address signal based on said command, and also asserting said control signal when said command is said special command;

a first register group including said plural registers, for receiving said read address signal, and outputting stored data of said plural registers selectively as said read data, based on said read address signal;

a second register group having a copy reference register for storing a copy of said reference stored data in said reference register in said plural registers, and a copy addition register for storing a copy of said addition stored data of said addition register in said plural registers, for outputting stored data of said copy reference register as said reference stored data, and stored data of said copy addition register as said addition stored data at all times; and

a program counter for receiving said control signal and said comparative result signal, and outputting a program count value for specifying an address of the command presently executing, based on said comparative result signal, when said control signal is asserted.

13. The computer of claim 12,

wherein said special command further specifies a predetermined number for additions;

said control means further comprises outputs for outputting said predetermined number for additions when said command is said special command; and

wherein said data operation section further comprising an adder for generating said comparative data by adding said predetermined number for additions to said addition stored data.

14. The computer of claim 13, wherein said control means comprises outputs for writing said comparative data into said addition register and said copy addition register, by outputting a write address signal for indicating to write said operation result into said addition register and said copy addition register to said first and second register groups, when said command is said special command.

15. The computer of claim 5,

wherein said special command specifies a register out of said plural registers that is to be used as an addition register, said data read section specifies said addition register out of said plural registers, on the basis of a register specifying value, when said command is said special command, and further outputs addition stored data which is stored data in said addition register;

and

said comparative data is generated based on said addition stored data.

6. A computer comprising:

a data read section including plural registers for outputting stored data of said plural registers selectively as read data based on a command obtained from outside; and

a data operation unit for operating according to said read data and outputting an operation result;

wherein said data read section specifies a reference register out of said plural registers when said command is a special command, and for outputting reference stored data which is stored data in said reference register as said read data; and

wherein said data operation section comprises data comparative means for comparing said reference stored data with comparative data to output a comparative result signal,

wherein said data read section comprises;

control means for outputting a read address signal based on said command, and asserting a special command signal when said command is a special command; and

a register group including said plural registers, for receiving said read address signal, and outputting stored data of said plural registers selectively as said read data based on said read address signal, wherein said register group further receives said special command signal, and outputs said reference stored data of said reference register as said read data regardless of said read address signal when said special command signal is asserted.

7. The computer of claim 6, wherein said data read section further asserts a control signal only when said command is said special command, said computer further comprising:

a program counter for receiving said control signal and said comparative result signal, and outputting a program count value for specifying an address of the command presently being executed, based on said comparative result signal, when said control signal is asserted.

16. A computer comprising:

a data read section including plural registers for outputting stored data of said plural registers selectively as read data based on a command obtained from outside, wherein said data read section preliminarily specifies at least two registers out of said plural registers as an addition register group, and preliminarily specifies at least two registers out of said plural registers other than said addition register group as a reference register group, said command includes a special command including a first register specifying value for specifying an addition register in said addition register group, and a second register specifying value for specifying a reference register in said reference register group;

a data operation section for operating according to said read data to output an operation result;

wherein said data read section specifies said addition register in said addition register group based on said first register specifying value, when said command is said special command, specifying said reference register in said reference register group based on said second register specifying value, and outputting as said read data both addition stored data which is stored data of said addition register and reference stored data which is stored data of said reference register; and

wherein said data operation section comprises data comparative means for comparing

     1) comparative data generated by using said addition data, with

     2) said reference stored data, to output a comparative result signal.