Circuit with switch controller that signals switch control input to close switch upon completing request acknowledgment of connection request from data transfer port

• US 5,875,353 A
• Filed: 06/07/1995
• Issued: 02/23/1999
• Est. Priority Date: 06/17/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): WANG, ALBERT C
• Application Number:
  US08/485,741
• Time in Patent Office: 1,357 Days
• Field of Search: 395/500, 395/550, 395/309, 395/726, 395/775, 395/850, 395/849, 395/311, 395/858, 455/11.1, 370/362, 370/360
• US Class Current: 710/38
• CPC Class Codes: G01R 31/2815 Functional tests, e.g. boundary scans, using the normal I/O contacts contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00
• CPC Class Codes: G01R 31/31722 Addressing or selecting of test units, e.g. transmission protocols for selecting test units for scan test G01R31/318558
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

A protocol and associated circuitry operable for efficiently extending serial bus capability in system environments is disclosed. The protocol is designed to coexist and be fully compatible with existing serial bus approaches, and in particular an example of application of the invention to a backplane system utilizing the 1149.1 IEEE standard serial bus is detailed. The circuitry and protocol required to couple any one of the boards on the backplane to the serial bus master without modifying the existing serial bus protocol, without adding additional signals, and without affecting the throughput rate of the serial bus is described. The invention advantageously allows the serial bus master to select, communicate with, and deselect backplane boards so that high level test functions may be simultaneously executed and monitored. Additional preferred embodiments are also disclosed.

Claims

1. Electrical circuitry, comprising:

a data transfer port;

a switch to make selectively a desired connection within said electrical circuitry, said switch having a control input to control opening and closing thereof; and

a switch controller coupled to said port and having an output which, in response to a connection request received at said port, applies a request acknowledgement to said port, said switch controller having a further output which is connected to said control input of said switch and which, in response to completion of said request acknowledgement, signals said control input to close said switch.

2. Electrical circuitry, comprising:

first and second data transfer ports;

a switch connected between said first and second ports, said switch having a control input to control opening and closing thereof; and

a switch controller coupled to said first port and having an output which, in response to a connection request received at said first port, applies a request acknowledgement to said first port, said switch controller having a further output which is connected to said control input of said switch and which, in response to completion of said request acknowledgement, signals said control input to close said switch.

3. A method of closing a switch, comprising the steps of:

issuing a request to close the switch;

issuing a request acknowledgement in response to the request; and

closing the switch in response to completion of the request acknowledgement.

4. Electrical circuitry, comprising:

first and second data transfer ports connectable to one another and cooperable when connected to communicate therebetween according to a first communication protocol; and

acknowledgement circuitry coupled to said first port, said acknowledgement circuitry having an output which, in response to communication at said first port according to a second communication protocol, applies to said first port an acknowledge signal.

5. A method of operating data transfer ports, comprising the steps of:

applying to one of the ports a request according to a first communication protocol;

applying an acknowledgment signal to said one port in response to the request; and

communicating between the ports according to a second communication protocol.

6. An electrical system, comprising:

first and second data transfer ports;

first and second circuitries respectively connected to said first and second ports;

a switch connected between said first and second ports, said switch having a control input to control opening and closing thereof;

a switch controller coupled to said first port and having an output which, in response to a connection request received at said first port, applies a request acknowledgement to said first port, said switch controller having a further output which is connected to said control input of said switch and which, in response to completion of said request acknowledgement, signals said control input to close said switch; and

said first and second circuitries operable to communicate therebetween when said switch is closed, said first circuitry operable to provide said connection request and receive said request acknowledgement.

7. An electrical system, comprising:

first and second data transfer ports selectively connectable to and disconnectable from one another;

first and second circuitries respectively connected to said first and second ports, said first and second circuitries cooperable to communicate therebetween according to a first communication protocol when said ports are connected;

acknowledgement circuitry coupled to said first port, said acknowledgement circuitry having an output which, in response to communication at said first port according to a second communication protocol, applies to said first port an acknowledge signal; and

said first circuitry operable to provide at said first port said communication according to said second communication protocol.