DRAM/SRAM with uniform access time using buffers, write back, address decode, read/write and refresh controllers

• US 5,875,452 A
• Filed: 12/12/1996
• Issued: 02/23/1999
• Est. Priority Date: 12/21/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Katayama, Yasunao, Sato, Akashi
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Langjahr, David
• Application Number:
  US08/764,809
• Time in Patent Office: 803 Days
• Field of Search: 711/143, 711/105, 395/445, 395/562, 207/104
• US Class Current: 711/105
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A DRAM is provided that can carry out data reads or writes in a constant and short access time regardless of the timing with which the reads or writes, or refreshing are executed. When requests for reads from or writes to burst data are continuously input, row decoding (RD) and column decoding (CD) by a row decoder 42 and a column decoder 52, an array access (AR) and precharging (PR) by a data line driver 24, a bit switch 26, and a sense amplifier 28, and data transfer (TR) by a write buffer 52 and a read buffer 54 are executed in parallel in a pipelined manner. When the time has come to refresh a DRAM array 22, a refresh address held in a refresh controller 40 is output while the burst data is being transferred, and a series of refreshing operations comprising (RD), (AR), and (PR) is performed.

Claims

1. A memory system comprising:

a DRAM array having a plurality of DRAM cells each of said DRAM cells connected to a bit line;

a data buffer;

a read/write controller for in response to a read request specifying a first address area of said DRAM array, reading data composed of a plurality of unit data from said first address area via said bit line, and storing the read data into said data buffer, and sending out said data from said data buffer, and for, in response to a write request specifying a second address area of said DRAM array, storing data composed of a plurality of unit data for said second address area into said data buffer from the outside, and writing said data which has been stored in said data buffer into said second address area of said DRAM array via said bit line, and for scheduling the writing and reading for said DRAM array so that the writing and reading do not overlap with a precharge for said bit line; and

a refresh controller for scheduling a refresh for said DRAM array and a precharge for said bit line so that the writing and reading and said precharge by said read/write controller do not overlap with said refresh and said precharge for said bit line.

2. The memory system of claim 1 wherein the refresh controller sequentially refreshes each area of the DRAM array, the refresh controller immediately refreshes a specified area of the DRAM array to be refreshed and precharges the bit line if the read/write controller does not carry out a data read from and any data write to the DRAM array and does not precharge the bit line within a predetermined period of time at an arrival of time to refresh the DRAM array time, and if the read/write controller carry out at least one of the data read from and the data write to the DRAM array or precharge the bit line within said predetermined period of time, said refresh controller holds an address of said specified area and in response to a situation in which the read/write controller does not carry out any data read from and any data write to the DRAM array and does not precharge the bit line, the refresh controller refreshes said specified area and precharges the bit line according to said held address.

3. The memory system of claim 2 wherein the data buffer includes a read and a write buffer so that when a data write is carried out, the read/write controller saves in an address buffer the addresses of an area to which the data is written and holds in the data buffer write data sequentially transferred from an external source on a unit data basis and if a data read is externally requested at the same time when or before the transfer of write data from the external source is completed, the data is read from the DRAM array and held in said read buffer, and while read data is being sequentially transferred to the external destination on a unit data basis or when the next request is a data write, said write data is written to the DRAM array based on the addresses saved in said address buffer.

4. The memory system of claim 3 wherein the read/write controller includes a data transfer section and an address decode section for transferring data between the data buffer and an external device the data transfer section and the address decode section operate in parallel so that both the read/write controller and the refresh controller use the same address decode section for decoding the addresses of an area from or to which data is read or written or which is to be refreshed and the same array access section for reading or writing data from or to the specified area of the DRAM array corresponding to addresses of an area from or to which data is read or written or which is to be refreshed and the same array access section for reading or writing data from or to the specified area of the DRAM array corresponding to the addresses decoded by said address decode section, refreshing the specified area, or precharging the bit line of the DRAM array.

5. A memory system comprising:

a plurality of DRAM cells;

a storage means for temporarily storing data having a number of storage cells;

a refresh controller operative upon the arrival of the time to refresh the DRAM array for refreshing the DRAM array while data is not being read from or written, to the DRAM array;

a read/write controller operative upon an external request for a data read from or a data write to a specified area of the DRAM array being refreshed by the refresh controller, for reading data from a specified area of the DRAM array, transferring to an external destination the data read from the specified area, and storing it in the storage means, or using write data transferred from the external source to rewrite the data read front the specified area and storing the rewritten data in the storage means if the data corresponding to the specified area of the DRAM array is not stored in the storage means, and if the data corresponding to the specified area of the DRAM array is stored in the storage means, executing a read or a write of the data stored in the storage means and corresponding to the specified area; and

a write back controller for writing back the data stored in the storage means to the corresponding area of the DRAM array after the refreshing of the DRAM array by the refresh controller has been completed.

6. The memory system according to claim 5 in which the number of storage cells in the storage means constitute a single storage cell column which is the same as the number of DRAM cells in a single DRAM cell column of the DRAM array.

7. The memory system according to claim 6 in which the refresh controller sequentially refreshes each of the plurality of DRAM arrays.

8. The memory system of claim 7 in which if an external request for a data write to a specified area of the DRAM array being refreshed by the refresh controller and the data corresponding to the specified area of the DRAM array is not stored in the storage means, then the data is read from the specified area of the DRAM array by the read/write controller and the data read from the specified area is rewritten using write data transferred from the external source in order to store the rewritten data in the storage means and to write it to the specified area of the DRAM array.

9. The memory system according to claim 7 in which if a request for a data read from or a data write to a specified area of the DRAM array being refreshed by the refresh controller is received, the read/write controller can determine whether or not the data corresponding to the specified area is stored in the storage means.

10. The memory system of claim 7 wherein if the read/write controller has read or written data from or to the DRAM array being refreshed by the refresh controller wherein the read/write controller stores a first identification information for identifying that area of the DRAM array from or to which data has been read or written to determine whether or not the data in the specified area to which the read or write has been executed is stored in the storage means based on the first identification information.

11. The memory system of claim 10 in which the write back controller can carry out write backs of all the data stored in the storage means, based on the first identification information, as a result of reads or writes by the read/write controller, and clear the first identification information after the completion of the write back.

12. The memory system of claim 7 further includes a plurality of DRAM arrays wherein the read/write controller may read or write data from or to one DRAM array while refreshing another DRAM array.

13. The memory system of claim 7 in which, if the refresh controller and the read/write controller attempt with the same timing to refresh the specified area of the DRAM array and to carry out a data read or write, respectively, then the read/write controller reads or writes data from or to the specified area of the DRAM array, and the refresh controller omits the refreshing of the specified area of the DRAM array.

14. The memory system of claim 13 characterized in that if said read/write controller has executed a write only to data stored in said storage means, it stores a second identification information for identifying contaminated data occurring due to said write wherein the write back controller writes back contaminated data based on the second identification information.

15. The memory system of claim 14 characterized in that after writing back the contaminated data based on said second identification information, said write back controller clears said second identification information.

16. The memory system of claim 12, further including a write back line for writing back data from said storage means to said DRAM array wherein if the read/write controller is reading or writing data from or to a DRAM array that is different from the DRAM array to which data is to be written back, the write back controller uses the write back line to execute a write back to the DRAM array to which data is to be written back.

17. The memory system according to claim 7 wherein if the data corresponding to an area of the DRAM array which has been specified by a data write request is stored in the storage means as the data to be written back by the write back controller, the read/write controller executes a write to the data to be written back which is stored in the storage means, and the write back controller writes back the data to be written back on which the write has been executed by the read/write controller, from the storage means to the DRAM array in the same cycle in which the read/write controller writes the data.

18. The memory system of claim 17 wherein the storage means comprises SRAMs.