DRAM/SRAM with uniform access time using buffers, write back, address decode, read/write and refresh controllers
First Claim
1. A memory system comprising:
- a DRAM array having a plurality of DRAM cells each of said DRAM cells connected to a bit line;
a data buffer;
a read/write controller for in response to a read request specifying a first address area of said DRAM array, reading data composed of a plurality of unit data from said first address area via said bit line, and storing the read data into said data buffer, and sending out said data from said data buffer, and for, in response to a write request specifying a second address area of said DRAM array, storing data composed of a plurality of unit data for said second address area into said data buffer from the outside, and writing said data which has been stored in said data buffer into said second address area of said DRAM array via said bit line, and for scheduling the writing and reading for said DRAM array so that the writing and reading do not overlap with a precharge for said bit line; and
a refresh controller for scheduling a refresh for said DRAM array and a precharge for said bit line so that the writing and reading and said precharge by said read/write controller do not overlap with said refresh and said precharge for said bit line.
1 Assignment
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Accused Products
Abstract
A DRAM is provided that can carry out data reads or writes in a constant and short access time regardless of the timing with which the reads or writes, or refreshing are executed. When requests for reads from or writes to burst data are continuously input, row decoding (RD) and column decoding (CD) by a row decoder 42 and a column decoder 52, an array access (AR) and precharging (PR) by a data line driver 24, a bit switch 26, and a sense amplifier 28, and data transfer (TR) by a write buffer 52 and a read buffer 54 are executed in parallel in a pipelined manner. When the time has come to refresh a DRAM array 22, a refresh address held in a refresh controller 40 is output while the burst data is being transferred, and a series of refreshing operations comprising (RD), (AR), and (PR) is performed.
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Citations
18 Claims
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1. A memory system comprising:
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a DRAM array having a plurality of DRAM cells each of said DRAM cells connected to a bit line; a data buffer; a read/write controller for in response to a read request specifying a first address area of said DRAM array, reading data composed of a plurality of unit data from said first address area via said bit line, and storing the read data into said data buffer, and sending out said data from said data buffer, and for, in response to a write request specifying a second address area of said DRAM array, storing data composed of a plurality of unit data for said second address area into said data buffer from the outside, and writing said data which has been stored in said data buffer into said second address area of said DRAM array via said bit line, and for scheduling the writing and reading for said DRAM array so that the writing and reading do not overlap with a precharge for said bit line; and a refresh controller for scheduling a refresh for said DRAM array and a precharge for said bit line so that the writing and reading and said precharge by said read/write controller do not overlap with said refresh and said precharge for said bit line. - View Dependent Claims (2, 3, 4)
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5. A memory system comprising:
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a plurality of DRAM cells; a storage means for temporarily storing data having a number of storage cells; a refresh controller operative upon the arrival of the time to refresh the DRAM array for refreshing the DRAM array while data is not being read from or written, to the DRAM array; a read/write controller operative upon an external request for a data read from or a data write to a specified area of the DRAM array being refreshed by the refresh controller, for reading data from a specified area of the DRAM array, transferring to an external destination the data read from the specified area, and storing it in the storage means, or using write data transferred from the external source to rewrite the data read front the specified area and storing the rewritten data in the storage means if the data corresponding to the specified area of the DRAM array is not stored in the storage means, and if the data corresponding to the specified area of the DRAM array is stored in the storage means, executing a read or a write of the data stored in the storage means and corresponding to the specified area; and a write back controller for writing back the data stored in the storage means to the corresponding area of the DRAM array after the refreshing of the DRAM array by the refresh controller has been completed. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification