Semiconductor integrated circuit processing wafer having a PECVD material layer of improved thickness uniformity

• US 5,876,838 A
• Filed: 12/27/1996
• Issued: 03/02/1999
• Est. Priority Date: 05/09/1994
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Mallon, Thomas G.
• Primary Examiner(s): MULVANEY, ELIZABETH EVANS
• Application Number:
  US08/774,948
• Time in Patent Office: 795 Days
• Field of Search: 428/195, 428/209, 428/210, 428/213, 428/901, 438/699
• US Class Current: 428/195.1
• CPC Class Codes: C23C 16/509 using internal electrodes
• CPC Class Codes: C23C 16/52 Controlling or regulating the coating process C23C16/45557, C23C16/279 take precedence
• CPC Class Codes: H01J 37/32009 Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources plasma generation in general H05H1/24
• CPC Class Codes: H01J 37/32541 Shape
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
• CPC Class Codes: Y10T 428/24917 including metal layer
• CPC Class Codes: Y10T 428/24926 including ceramic, glass, porcelain or quartz layer
• CPC Class Codes: Y10T 428/2495 Thickness [relative or absolute]

Abstract

A semiconductor integrated circuit is made by a process including the formation on a surface of a semiconductor integrated circuit processing wafer of a layer of material applied to the wafer by plasma enhanced chemical vapor deposition (PECVD). The layer of material may include plural sub-layers, the thicknesses of which are additive to result in the thickness of the layer of material itself. The sub-layers of material may have non-uniform thicknesses across a dimension of the processing wafer because of compromises in the process which are necessary to control various parameters of the material layer other than its thickness. These non-uniformities of thickness of the sub-layers may be controlled to offset one another so that the resulting layer of material has a substantially uniform thickness across the dimension of the processing wafer. A method, and apparatus for practicing the method, are set forth along with an explanation of how particular geometric factors of electrodes used in the PECVD process affect the resulting thickness non-uniformities. The thickness non-uniformities of the sub-layers may also be largely abated by use of the invention in a predictive-corrective fashion. A similar predictive-corrective method and resulting apparatus is set forth for gas plasma etching of an existing layer of material on a semiconductor integrated circuit processing wafer.

Claims

1. A semiconductor integrated circuit processing wafer, comprising:

a substrate;

a PECVD layer on said substrate;

said PECVD layer comprising plural PECVD sub-layers; and

said plural sub-layers having compensating profiles of non-uniform as-deposited thicknesses across at least a substantial portion of said substrate, said compensating profiles are additive to result in said PECVD layer having a generally uniform as-deposited thickness across said at least a substantial portion of said substrate.

2. A wafer of claim 1 wherein said at least a substantial portion of said substrate is the entire extent of said substrate.

3. A wafer of claim 1 wherein said layer has its top surface being substantially parallel with an underlying surface of said substrate.

4. The wafer of claim 3 wherein said top surface of said layer is substantially flat across said at least a substantial portion of said substrate.

5. The wafer of claim 1 wherein said plural sub-layers include a first as-deposited sub-layer which has an as-deposited convex surface across said at least a substantial portion of said substrate, and a second as-deposited sub- layer which has a complementary as-deposited concave surface thereon across said at least a substantial portion of said substrate.

6. The wafer of claim 5 wherein said first as-deposited sub-layer is thicker in the center of said first as-deposited sub-layer than near the periphery of said first as-deposited sub-layer, and said second as-deposited sub-layer is thicker near the periphery of said second as-deposited sub-layer than near the center of said second as-deposited sub-layer.

7. The wafer of claim 5 wherein said first as-deposited sub-layer is thicker over the center of said substrate than over the periphery of said substrate, and said second as-deposited sub-layer is thicker over the periphery of said substrate than over the center of said substrate.

8. The wafer of claim 1 wherein said plural as-deposited sub-layers comprise first and second as-deposited sub-layers;

said first and second as-deposited sub-layers together have anticipated non-uniform thicknesses across said at least a substantial portion of said substrate, and said sub-layers further comprise a third as-deposited PECVD sub-layer on said second as-deposited sub-layer such that said first, second and third as-deposited sub-layers together have a more uniform as-deposited thickness than that of said first and second as-deposited sub-layers together.

9. The wafer of claim 1 wherein said plural as-deposited sub-layers have compensating profiles of non-uniform as-deposited thicknesses across the entire extent of said substrate which are additive to result in said layer having a generally uniform as-deposited thickness across the extent of said substrate.

10. The wafer of claim 1 wherein said first as-deposited sub-layer has a concave surface across the length and width of said substrate, and said second as-deposited sub-layer has a complementary convex surface thereon across the length and width of said substrate.

11. The wafer of claim 10 wherein said first as-deposited sub-layer is thinner over the center of said substrate than over the periphery of said substrate, and said second as-deposited sub-layer is thinner over the periphery of said substrate than over the center of said substrate.

12. The wafer of claim 10 wherein said first as-deposited sub-layer is thinner in the center of said first as-deposited sub-layer than near the periphery of said first as-deposited sub-layer, and said second as-deposited sub-layer is thinner near the periphery of said second as-deposited sub-layer than near the center of said second as-deposited sub-layer.

13. The wafer of claim 1 wherein said first and second as-deposited sub-layers together have an anticipated as-deposited non-uniform thickness over the length and width of said substrate, and said sub-layers further comprise a third as-deposited sub-layer on said second as-deposited sub-layer such that said first, second and third as-deposited sub-layers have a more uniform as-deposited thickness than that of said first and second as-deposited sublayers together.

14. The wafer of claim 1 wherein said sub-layers are directly one on top of another.