Ultra-short channel recessed gate MOSFET with a buried contact

• US 5,877,056 A
• Filed: 01/08/1998
• Issued: 03/02/1999
• Est. Priority Date: 01/08/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Texas Instruments Acer Inc (Acer, Inc.)
• Inventors: Wu, Shye-Lin
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Gurley, Lynne A.
• Application Number:
  US09/004,448
• Time in Patent Office: 418 Days
• Field of Search: 438/291, 438/297, 438/299, 438/585, 438/589, 438/591, 438/595, 438/300
• US Class Current: 438/291
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

Following with the formation of pad insulator layer and a stacked layer stacked, a gate insulator is formed within the defined gate insulator space. A lightly doped region is doped and the stacked layer and the pad insulator layer is removed. A semiconductor layer is formed and a gate space is defined over the gate insulator through a spacer structure. An anti punchthrough region is formed followed by the formation of a first insulator layer. A gate filling is then formed to fill within the gate space. A portion of the first insulator layer is then removed. A step of doping a plurality of junction ions is applied. A second insulator layer is formed and a thermal process is then proceeded. Finally a metalization process is employed on the semiconductor substrate.

Claims

1. A method of forming a transistor in a semiconductor substrate, said semiconductor substrate having an isolation region, said method comprising the steps of:

forming a pad insulator layer over said semiconductor substrate;

forming a stacked layer stacked over said pad insulator layer;

removing a portion of said stacked layer for having an gate insulator space in said stacked layer to said pad insulator layer;

forming a gate insulator within said gate insulator space over said semiconductor substrate;

doping a lightly doped region with a first concentration of a first dopant type in said semiconductor substrate uncovered by said gate insulator and said isolation region;

removing said stacked layer and said pad insulator layer;

forming a semiconductor layer over said semiconductor substrate;

removing a portion of said semiconductor layer over said gate insulator to define a space over said gate insulator;

forming spacer structure in said space on a sidewall portion of said semiconductor layer;

removing a portion of said gate insulator for having a gate space over said semiconductor substrate;

doping an anti punchthrough region in said semiconductor substrate under said gate space with a second concentration of a second dopant type;

forming a first insulator layer on said semiconductor substrate under said gate space and on said semiconductor layer;

forming a gate filling to fill within said gate space;

removing a portion of said first insulator layer which is uncovered by said gate filling;

doping a plurality of junction ions with a third concentration of a third dopant type into said semiconductor layer;

forming a second insulator layer over said semiconductor substrate;

performing a thermal process to said semiconductor substrate; and

performing a metalization process on said semiconductor substrate.

2. The method of claim 1, wherein said semiconductor substrate comprises a silicon substrate.

3. The method of claim 1, wherein said pad insulator layer comprises a silicon oxide layer which is thermally grown in an oxygen containing ambient on said semiconductor substrate with a thickness of about 50 angstroms to 400 angstroms.

4. The method of claim 1, wherein said stacked layer comprises a silicon nitride layer deposited with a thickness of about 300 angstroms to 2000 angstroms.

5. The method of claim 1, wherein said gate insulator comprises an oxide insulator grown from said semiconductor substrate in a thermal ambient containing oxygen, with a thickness of about 1000 angstroms to 4000 angstroms.

6. The method of claim 1, wherein said semiconductor layer comprises an undoped amorphous silicon layer forming by a chemical vapor deposition process with a thickness of about 300 angstroms to 3000 angstroms.

7. The method of claim 1, wherein said semiconductor layer comprises an undoped polysilicon layer forming by a chemical vapor deposition process with a thickness of about 300 angstroms to 3000 angstroms.

8. The method of claim 1, wherein said step of doping said lightly doped region is performed with a first ion implanting process at an energy between about 40 KeV to 300 KeV to have a dose between about 5E12 to 5E14 atoms/cm² for said lightly doped region, said first dopant type being selected from the group consisting of an arsenic containing dopant and a phosphorous containing dopant.

9. The method of claim 1, wherein said step of doping said anti punchthrough region is performed with a second ion implanting process at an energy between about 0.5 KeV to 30 KeV to have a dose between about 5E11 to 5E13 atoms/cm², said second dopant type being a boron containing dopant.

10. The method of claim 1, wherein said step of doping said junction region is performed with a first ion implanting process at an energy between about 5 KeV to 100 KeV to have a dose between about 5E14 to 5E16 atoms/cm², said third dopant type being selected from the group consisting of an arsenic containing dopant and a phosphorous containing dopant.

11. The method of claim 1, wherein said step of doping said lightly doped region is performed with a first ion implanting process at an energy between about 40 KeV to 300 KeV to have a dose between about 5E12 to 5E14 atoms/cm² for said lightly doped region, said first dopant type being a boron containing dopant.

12. The method of claim 1, wherein said step of doping said anti punchthrough region is performed with a second ion implanting process at an energy between about 0.5 KeV to 30 KeV to have a dose between about 5E11 to 5E13 atoms/cm², said second dopant type being selected from the group consisting of an arsenic containing dopant and a phosphorous containing dopant.

13. The method of claim 1, wherein said step of doping said junction region is performed with a first ion implanting process at an energy between about 5 KeV to 100 KeV to have a dose between about 5E14 to 5E16 atoms/cm², said third dopant type being a boron containing dopant.

14. The method of claim 1, wherein said spacer structure is formed by sequentially depositing and etching back of a nitride layer.

15. The method of claim 1, wherein said first insulator layer comprises an oxynitride layer with a thickness between about 20 angstroms to about 250 angstroms, said oxynitride layer being grown thermally from said semiconductor substrate and said semiconductor layer in a nitrogen and oxygen containing ambient.

16. The method of claim 1, wherein said gate filling is formed by sequentially depositing and etching back an undoped polysilicon layer.

17. The method of claim 1, wherein said second insulator layer comprises an oxide layer formed by a chemical vapor deposition.

18. The method of claim 1, wherein said thermal process comprises a rapid thermal process (RTP) performed with a temperature between about 700°

C. to about 1100°

C. for driving said plurality of junction ions into said semiconductor substrate to form a junction region, and for condensing said second insulator layer.

19. A method of forming a transistor in a semiconductor substrate, said semiconductor substrate having an isolation region, said method comprising the steps of:

forming a pad insulator layer over said semiconductor substrate;

forming a stacked layer stacked over said pad insulator layer;

removing a portion of said stacked layer for having an oxide insulator space in said stacked layer to said pad insulator layer;

forming an oxide insulator within said oxide insulator space over said semiconductor substrate;

doping a lightly doped region with a first concentration of a first dopant type in said semiconductor substrate uncovered by said oxide insulator and said isolation region;

removing said stacked layer and said pad insulator layer;

forming a silicon layer over said semiconductor substrate;

removing a portion of said silicon layer over said oxide insulator to define a space over said oxide insulator;

forming spacer structure in said space on a side wall portion of said silicon layer;

removing a portion of said oxide insulator for having a gate space over said semiconductor substrate;

doping an anti punchthrough region in said semiconductor substrate under said gate space with a second concentration of a second dopant type;

forming a first insulator layer on said semiconductor substrate under said gate space and on said silicon layer;

forming a gate filling to fill within said gate space;

removing a portion of said first insulator layer which is uncovered by said gate filling;

doping a plurality of junction ions with a third concentration of a third dopant type into said silicon layer;

forming a second insulator layer over said semiconductor substrate;

performing a thermal process to said semiconductor substrate; and

performing a metalization process on said semiconductor substrate for forming a set of connections to said silicon layer.

20. The method of claim 19, wherein said semiconductor substrate comprises a silicon substrate.

21. The method of claim 19, wherein said pad insulator layer comprises a silicon oxide layer which is thermally grown in an oxygen containing ambient on said semiconductor substrate with a thickness of about 50 angstroms to 400 angstroms.

22. The method of claim 19, wherein said stacked layer comprises a silicon nitride layer deposited with a thickness of about 300 angstroms to 2000 angstroms.

23. The method of claim 19, wherein said oxide insulator is grown from said semiconductor substrate in a thermal ambient containing oxygen, with a thickness of about 1000 angstroms to 4000 angstroms.

24. The method of claim 19, wherein said silicon layer comprises an undoped amorphous silicon layer forming by a chemical vapor deposition process with a thickness of about 300 angstroms to 3000 angstroms.

25. The method of claim 19, wherein said silicon layer comprises an undoped polysilicon layer forming by a chemical vapor deposition process with a thickness of about 300 angstroms to 3000 angstroms.

26. The method of claim 19, wherein said step of doping said lightly doped region is performed with a first ion implanting process at an energy between about 40 KeV to 300 KeV to have a dose between about 5E12 to 5E14 atoms/cm² for said lightly doped region, said first dopant type being selected from the group consisting of an arsenic containing dopant and a phosphorous containing dopant.

27. The method of claim 19, wherein said step of doping said anti punchthrough region is performed with a second ion implanting process at an energy between about 0.5 KeV to 30 KeV to have a dose between about 5E11 to 5E13 atoms/cm², said second dopant type being a boron containing dopant.

28. The method of claim 19, wherein said step of doping said junction region is performed with a first ion implanting process at an energy between about 5 KeV to 100 KeV to have a dose between about 5E14 to 5E16 atoms/cm², said third dopant type being selected from the group consisting of an arsenic containing dopant and a phosphorous containing dopant.

29. The method of claim 19, wherein said step of doping said lightly doped region is performed with a first ion implanting process at an energy between about 40 KeV to 300 KeV to have a dose between about 5E12 to 5E14 atoms/cm² for said lightly doped region, said first dopant type being a boron containing dopant.

30. The method of claim 19, wherein said step of doping said anti punchthrough region is performed with a second ion implanting process at an energy between about 0.5 KeV to 30 KeV to have a dose between about 5E11 to 5E13 atoms/cm², said second dopant type being selected from the group consisting of an arsenic containing dopant and a phosphorous containing dopant.

31. The method of claim 19, wherein said step of doping said junction region is performed with a first ion implanting process at an energy between about 5 KeV to 100 KeV to have a dose between about 5E14 to 5E16 atoms/cm², said third dopant type being a boron containing dopant.

32. The method of claim 19, wherein said spacer structure is formed by sequentially depositing and etching back a nitride layer.

33. The method of claim 19, wherein said first insulator layer comprises an oxynitride layer with a thickness between about 20 angstroms to about 250 angstroms, said oxynitride layer being grown thermally from said semiconductor substrate and said semiconductor layer in a nitrogen and oxygen containing ambient.

34. The method of claim 19, wherein said gate filling is formed by sequentially depositing and etching back of an undoped polysilicon layer.

35. The method of claim 19, wherein said second insulator layer comprises an oxide layer formed by a chemical vapor deposition.

36. The method of claim 19, wherein said thermal process comprises a rapid thermal process (RTP) performed with a temperature between about 700°

C. to about 1100°

C. for driving said plurality of junction ions into said semiconductor substrate to form a junction region, and for condensing said second insulator layer.