Structure to provide effective channel-stop in termination areas for trenched power transistors

• US 5,877,528 A
• Filed: 03/03/1997
• Issued: 03/02/1999
• Est. Priority Date: 03/03/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Megamos Corporation
• Inventors: So, Koon Chong
• Primary Examiner(s): FAHMY, WAEL M
• Application Number:
  US08/810,546
• Time in Patent Office: 729 Days
• Field of Search: 257/329, 257/330, 257/331, 257/334, 257/341, 257/372, 257/376, 257/345, 257/396, 257/397, 257/398, 257/399, 257/400
• US Class Current: 257/341
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention discloses a trenched DMOS device supported on a substrate of a first conductivity type including a core cell area which includes at least a trenched DMOS cell having a gate disposed in a trench and a drain region disposed in the substrate, the substrate further includes a termination area which includes at least a channel-stop trench. The trenched DMOS cell includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches in the substrate. The trenched DMOS cell further includes a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface surrounding the source region adjacent the trenches in the substrate. The trenched DMOS device further includes an insulating layer lining the trenches and a conductive material filling the trenches. The channel stop trench in the termination area with the conductive material filled therein is in electrical contact with the drain region via a metal contact formed thereon wherein the channel stop trench filled with the conductive material is surrounded by and insulated from the substrate by the insulating layer lining the channel stop trench whereby a channel stop is formed therein.

Claims

1. A trenched DMOS device comprising:

a substrate of a first conductivity type including a core cell area which includes at least a trenched DMOS cell having a gate disposed in a trench opened from a top surface of said substrate and a drain region disposed in said substrate, said substrate further includes a termination area which includes at least a channel-stop trench;

a source region of said first conductivity type extending from said top surface of said substrate adjacent to said trench in said substrate;

a body region of a second conductivity type of opposite polarity from said first conductivity type, said body region extends from said top surface surrounding said source region adjacent said trench in said substrate; and

an insulating layer lining said trench and a conductive material filling said trench;

said channel stop trench in said termination area padded by said insulating layer with said conductive material filled therein further includes an adjacent body-doped region and a metal layer thereon for electrically connecting said channel stop trench to said adjacent body region;

said metal layer shorting said channel stop trench to said drain region via said body-doped region for ternmnating a depletion channel.

2. The trenched DMOS device of claim 1 wherein:

said substrate and said source region of said first conductivity type is of a p-type conductivity and said body region of said second conductivity type is of a n-type conductivity.

3. The trenched DMOS device of claim 1 wherein:

said substrate and said source region of said first conductivity type is of a n-type conductivity and said body region of said second conductivity type is of a p-type conductivity.

4. The trenched DMOS device of claim 1 further comprising:

said conductive material filling said trenches is a polycrystalline silicon material.

5. A trenched transistor comprising:

a substrate of a first conductivity type including a core cell area which includes at least a cell having a gate disposed in a trench and a drain region disposed in said substrate, said substrate further includes a termination area includes at least a channel-stop trench;

an insulating layer lining said trenches and a conductive material filling said trench;

said channel stop trench in said termination area padded by said insulating layer with said conductive material filled therein further includes an adjacent body-doped region and a metal layer thereon for electrically connecting said channel stop trench to said adjacent body region;

said metal layer shortening said channel stop trench to said drain region via said body-doped region for terminating a depletion channel.

6. The trenched transistor of claim 5 wherein:

said conductive material filling said trenches is a polycrystalline silicon material.

7. The trenched transistor of claim 5 wherein:

said cell includes a source region of said first conductivity type extending from said top surface of said substrate adjacent to said trenches in said substrate; and

said trenched transistor cell further includes a body region of a second conductivity type of opposite polarity from said first conductivity type, said body region extends from a top surface of said substrate surrounding said source region adjacent to said trenches in said substrate.

8. The trenched transistor of claim 7 wherein:

said substrate and said source region of said first conductivity type is of a p-type conductivity and said body region of said second conductivity type is of a n-type conductivity.

9. The trenched transistor device of claim 7 wherein:

said substrate and said source region of said first conductivity type is of a n-type conductivity and said body region of said second conductivity type is of a p-type conductivity.