Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation
First Claim
1. An integrated circuit structure comprising a metal-oxide-silicon (MOS) device comprising:
- a) a gradient doped profile region provided in a semiconductor substrate by implantation with a single dopant, said gradient doped profile region extending from a heavily doped source/drain region in said substrate to a channel region in said substrate beneath a gate electrode of said MOS device, with the portion of said gradient doped profile region adjacent said channel region having a dopant level of about 5×
1013 dopant atoms/cm2 equivalent to that of a conventional lightly doped drain (LDD) region, with the remainder of said gradient doped profile region in said substrate having a dopant level gradually increasing from said dopant level equivalent to that of a conventional LDD region at said channel region up to a higher dopant level below the dopant level of said heavily doped source/drain region; and
b) said gate electrode having a sidewall which is tapered inwardly at its base adjacent said substrate to thereby provide formation of said gradient doped profile region in said substrate beneath said tapered wall of said gate electrode when said substrate and said gate electrode are subject to an implantation by an ion beam perpendicular to said substrate.
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Abstract
A novel integrated circuit structure, and process for making same, is disclosed wherein a tapered or gradient doped profile region is provided in a semiconductor substrate between the heavily doped drain region and the channel region in the substrate comprising an MOS device. In the process of the invention, a re-entrant or tapered gate electrode, resembling an inverted trapezoid, is used as a mask during a first doping step at a dosage level higher than normally used to form a conventional LDD region. This doping step forms a doped region having a dopant gradient which gradually increases in dosage level with distance from the channel region. Conventional oxide spacers may then be formed on the sidewalls of the gate electrode followed by conventional high level doping to form the heavily doped source and drain region in the unmasked portions of the substrate between the oxide spacers and the field oxide isolation. Since the doped region beneath the oxide spacers includes a gradient doped profile region, with the lightest level of dopant adjacent the channel region (since more of the tapered gate electrode acted as a mask for the initial implantation), the overall dosage level used in the first implantation step to form the gradient doped profile region may be higher than the dosage level conventionally used to form a conventional LDD region. The resistance of the path between the heavily doped drain contact region and the channel region, which includes the gradient doped profile region, is therefore lower than the resistance of a conventional LDD region.
40 Citations
10 Claims
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1. An integrated circuit structure comprising a metal-oxide-silicon (MOS) device comprising:
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a) a gradient doped profile region provided in a semiconductor substrate by implantation with a single dopant, said gradient doped profile region extending from a heavily doped source/drain region in said substrate to a channel region in said substrate beneath a gate electrode of said MOS device, with the portion of said gradient doped profile region adjacent said channel region having a dopant level of about 5×
1013 dopant atoms/cm2 equivalent to that of a conventional lightly doped drain (LDD) region, with the remainder of said gradient doped profile region in said substrate having a dopant level gradually increasing from said dopant level equivalent to that of a conventional LDD region at said channel region up to a higher dopant level below the dopant level of said heavily doped source/drain region; andb) said gate electrode having a sidewall which is tapered inwardly at its base adjacent said substrate to thereby provide formation of said gradient doped profile region in said substrate beneath said tapered wall of said gate electrode when said substrate and said gate electrode are subject to an implantation by an ion beam perpendicular to said substrate. - View Dependent Claims (2, 3, 4)
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5. An integrated circuit structure comprising a metal-oxide-silicon (MOS) device in a semiconductor substrate doped by implantation with a single dopant to have a low resistance path formed by a gradient doped profile region extending from a heavily doped source/drain region in said substrate to a channel region in said substrate beneath a gate electrode of said MOS device comprising:
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a) a re-entrant gate electrode formed on said substrate over a gate oxide and a channel region formed in said substrate, said re-entrant gate electrode having an outward sidewall taper, with respect to the vertical axis of said gate electrode, ranging from about 5°
to about 30°
, whereby said taper provides a wider top of said gate electrode than its base;b) a doped source/drain contact region formed in said substrate spaced from said channel region; and c) a gradient doped profile region formed in said substrate and extending from said channel region to said doped source/drain region, said gradient doped profile region formed by implantation with a single dopant through said re-entrant gate electrode sidewall by an implantation beam perpendicular to said substrate, with the highest dopant level in said gradient doped profile region being adjacent said doped source/drain region, but less than that of said doped source/drain region, and with the lowest dopant level in said gradient profile doped region being adjacent said channel region and having a dopant level of about 5×
1013 dopant atoms/cm2 equivalent to that of a conventional lightly doped drain (LDD) region, to inhibit generation of electric fields in said substrate adjacent said channel region. - View Dependent Claims (6, 7, 8)
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9. An integrated circuit structure comprising a metal-oxide-silicon (MOS) device in a semiconductor substrate doped solely by implantation with a single dopant to have a low resistance path formed by a gradient doped profile region extending from a heavily doped source/drain region in said substrate to a channel region in said substrate beneath a gate electrode of said MOS device comprising:
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a) a re-entrant gate electrode formed on said substrate over a gate oxide and a channel region formed in said substrate, said re-entrant gate electrode having an outward sidewall taper, with respect to the vertical axis of said gate electrode, ranging from about 5°
to about 30°
, and extending outwardly from a narrow bottom of said gate electrode adjacent said substrate to a wide top of said gate electrode;b) a doped source/drain contact formed in said substrate spaced from said channel region; and c) a gradient doped profile region formed in said substrate and extending from said channel region to said doped source/drain region, said gradient doped profile region formed by implantation with a single dopant through said re-entrant gate electrode sidewall by an implantation beam perpendicular to said substrate, with the highest dopant level in said gradient doped profile region being adjacent said doped source/drain region and ranging from about 5 to 50 times greater than about 5×
1013 dopant atoms/cm2, the dopant level of a conventional lightly doped drain (LDD) region, but less than that of said doped source/drain region, with the lowest dopant level in said gradient profile doped region being adjacent said channel region and having a dopant level of about 5×
1013 dopant atoms/cm2 equivalent to that of said conventional LDD region, to inhibit generation of electric fields in said substrate adjacent said channel region. - View Dependent Claims (10)
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Specification