Resistance bridge and its use in conversion systems

• US 5,877,637 A
• Filed: 02/05/1996
• Issued: 03/02/1999
• Est. Priority Date: 02/05/1996
• Status: Expired due to Fees

• Current Assignee: Faramarz Sabouri, Frederick N. Trofimenkoff, James W. Haslett
• Original Assignee: Faramarz Sabouri, Frederick N. Trofimenkoff, James W. Haslett
• Inventors: Sabouri, Faramarz, Haslett, James W., Trofimenkoff, Frederick N.
• Primary Examiner(s): Le, Dinh
• Application Number:
  US08/596,955
• Time in Patent Office: 1,121 Days
• Field of Search: 327/100, 327/101, 327/164, 327/131, 327/172, 327/105, 327/135, 327/138, 327/588, 327/512, 327/509, 327/513, 327/336, 73/766, 73/23.21, 422/96, 341/157, 324/691
• US Class Current: 327/101
• CPC Class Codes: G01R 17/10 AC or DC measuring bridges

Abstract

An electrical network creates a differential voltage signal and comprises a plurality of first impedance elements of substantially equal values which are connected to form an impedance bridge. The impedance of at least one of the first impedance elements changes in response to at least one selected external condition to which the first impedance elements are exposed. The network also comprises a second impedance element which has two nodes. The second impedance element is connected at these nodes between a first pair of the first impedance elements. The differential voltages are measured between these nodes and between another node or nodes with magnitudes and signs being dependent upon the change in the impedance of the first impedance elements.

Claims

1. An electrical network for creating differential voltage signals comprising:

four impedance elements of substantially equal values, two of said four impedance elements connected at a first junction to form a first impedance pair and two others of said four impedance elements connected at a second junction to form a second impedance pair, each of said pairs having first and second ends, the impedance of at least one of said four impedance elements changing in response to an external force to which said four impedance elements are exposed, said first and second impedance pairs connected at said first ends;

a reference voltage coupled to said first junction of said first impedance pair;

a grounding voltage coupled to said second junction of the second impedance pair;

an additional impedance element having first and second nodes and having a value substantially less than said four impedance elements, said first node of said additional impedance element coupled to said second end of said first impedance pair and said second node of said second impedance element coupled to said second end of the said second impedance pair, creating a first differential voltage between a first voltage of said first end of said additional impedance element and said first ends of said first and second impedance pairs and a second differential voltage between a second voltage of the second node of said second impedance element and said first ends of said first and second impedance pairs;

switching means for alternatively selecting between said first and second differential voltages;

integrating means coupled to said first ends and said switching means and having an output for receiving said selected differential voltages and for producing an integrated output voltage with a value representing an integral of said selected differential voltages; and

a pulse-forming circuit coupled to said output of said integrating means for forming a series of digital pulses from said integrated output of said integrating means, said digital pulses fed back to control said switching means.

2. The electrical network of claim 1 wherein:

said integrating means produces said integrated output voltage having a ramped waveform and includes a first capacitor which is charged at a first rate proportional to said positive first differential voltage and discharged at a second rate proportional to said negative second differential voltage, said charging occurring during a first time interval and said discharging occurring during a second time interval;

said pulse-forming circuit includes level detection means having an output and an input for receiving a predetermined voltage level responsive to said integrating means output for causing a signal at said output of said detection means to switch alternatively between a first and second state when said value of said integrating means output voltage reaches said predetermined voltage level;

wherein said switching means is responsive to the output of said level detection means for switching the input of said integrating means between said positive first and negative second differential voltages.

3. The electrical network of claim 2 wherein said pulse-forming circuit further comprises:

a clock with a first period;

timing means for adjusting a second period of the output of said level detection means;

wherein said second period consisting of a sum of said integrating means charging and discharging intervals, and synchronizing means for synchronizing said output of said level detection means to said clock.

4. The electrical network of claim 3 wherein each of said four impedance elements has a value and said value of each of said four impedance elements is varied by temperature changes.

5. The electrical network of claim 3 wherein said timing means comprise a first flip-flop for adjusting said output period to an integer multiple of the first period of said clock.

6. The electrical network of claim 5 wherein said synchronizing means comprises a second flip-flop having an output which is synchronized to said clock.

7. The electrical network of claim 6 further includes bridge supply switching means respectively coupling said reference voltage and said grounding voltage to said first and second junctions for providing third and fourth differential voltages.

8. The electrical network of claim 7 wherein said bridge supply switching means are responsive to a control voltage.

9. The electrical network of claim 8 wherein said integrating means further has an transfer function and wherein said integrating means contains a second capacitor for removing a zero from said transfer function of said integrating means.

10. A Δ

R-to-digital conversion system comprising;

four impedance elements of substantially equal values, two of said four impedance elements connected at a first junction to form a first impedance pair and two others of said four impedance elements connected at a second junction to form a second impedance pair, each of said pairs having first and second ends, the impedance of at least one of said four impedance elements changing in response to an external force to which said four impedance elements are exposed, said first and second impedance pairs connected at said first ends;

a reference voltage connected to said first junction of said first impedance pair;

a grounding voltage coupled to said second junction of said second impedance pair;

an additional impedance element having first and second nodes and having a value substantially less than said four impedance elements, said first node of said additional impedance element coupled to said second end of said first impedance pair and said second node of said second impedance element coupled to said second end of the said second impedance pair, creating a first differential voltage between a first voltage of said first node of said additional impedance element and said first ends of said first and second impedance pairs and a second differential voltage between a second voltage of the second node of said second impedance clement and said first ends of said first and second impedance pairs;

switching means for alternatively selecting between said first and second differential voltages;

integrating means coupled to said first ends and said switching means and having an output for receiving said selected differential voltages to produce an output voltage with a value representing an integral of said selected differential voltages; and

a pulse-forming circuit coupled to said output of said integrating means for forming a series of digital pulses from said output of said integrating means, said digital pulses fed back to control said switching means;

bridge supply switching means respectively coupling said reference signal and said grounding voltage to said first and second junctions for providing third and fourth differential voltages.

11. The system of claim 10 wherein said pulse-forming circuit wherein:

said integrating means produces said output voltage having a ramped waveform and includes a first capacitor which is changed at a first rate proportional to said first differential voltage and discharged at a second rate proportional to said negative second differential voltage, said charging occurring during a first time interval and said discharging occurring during a second time interval;

said pulse-forming circuit includes level detection means having an output and an input for receiving a predetermined voltage level responsive to said integrating means output for causing a signal at said output of said detection means to switch alternatively between a first and second state when said value of said integrating means output voltage reaches said predetermined voltage level; and

wherein said switching means is responsive to the output of said level detection means for switching the input of said integrating means between said first and second differential voltages.

12. The system of claim 11 wherein said pulse-forming circuit further comprises:

a clock with a first period;

timing means for adjusting a second period of the output of said level detection means;

said second period consisting of a sum of said integrating means charging and discharging intervals, and synchronizing means for synchronizing said output of said level detection means to said clock.

13. The system of claim 12 wherein said pulse-forming circuit is a pulse width modulator.

14. The system of claim 13 wherein said pulse-forming circuit is a voltage-to-frequency converter.

15. A method for converting a Δ

R into a digital signal comprising the steps;

providing four impedance elements of substantially equal values;

connecting two of said four impedance elements at a first junction to form a first impedance pair and connecting two others of said four impedance elements at a second junction to form a second impedance pair, said pairs having first and second ends;

connecting said first and second impedance element pairs at said first ends;

connecting a reference voltage to said first junction of said first impedance pair;

connecting a grounding voltage to said second junction of said second impedance pair;

exposing said four impedance elements to an external force;

providing an additional impedance element having first and second nodes and having a value substantially less than said four impedance elements;

coupling said first node of said additional impedance element to said second end of said first impedance pair and said second node of said additional impedance element to said second end of the said second impedance pair;

generating a first differential voltage signal between a first voltage of said first node of said additional impedance element and said first ends of said first and second impedance pairs and a second differential voltage between a second voltage of the second node of said additional impedance element and said first ends of said first and second impedance pairs;

alternatively selecting between said first and second differential voltages with a switching means;

producing an integrated output representing an integral of said selected differential voltages;

forming a series of digital pulses from said integrated output; and

feeding back said digital pulses to control said switching means.

16. A method for converting a Δ

R into a digital signal comprising the steps;

providing four impedance elements of substantially equal values;

connecting two of said four impedance elements at a first junction to form a first impedance pair and connecting two others of said four impedance elements at a second junction to form a second impedance pair, said pairs having first and second ends;

connecting said first and second impedance element pairs at said first ends;

connecting a reference voltage coupled to said first junction of said first impedance pair;

connecting a grounding voltage to said second junction of said second impedance pair;

exposing said four impedance elements to an external force;

providing an additional impedance element having first and second nodes and having a value substantially less than said four impedance elements;

coupling said first node of said additional impedance element to said second end of said first impedance pair and said second node of said additional impedance element to said second end of the said second impedance pair;

generating a first differential voltage signal between a first voltage of said first node of said additional impedance element and said first ends of said first and second impedance pairs and a second differential voltage between a second voltage of the second node of said additional impedance element and said first ends of said first and second impedance pairs;

alternatively selecting between said first and second differential voltages with a switching means;

producing an output signal representing an integral of said selected differential voltages;

forming a series of digital pulses from said output signal;

alternatively switching said reference voltage and said grounding voltage between said first junction and second junction; and

feeding back said digital pulses to control said switching means.

17. A Δ

R-to-digital conversion system comprising;

four impedance elements of substantially equal values, two of said four impedance elements connected at a first junction to form a first impedance pair and two others of said four impedance elements connected at a second junction to form a second impedance pair, each of said pairs having first and second ends, the impedance of at least one of said first impedance elements changing in response to an external force to which said four impedance elements are exposed, said first and second impedance pairs connected at said first ends;

a reference voltage coupled to said first junction of said first impedance pair; and

a grounding voltage coupled to said second junction of the second impedance pair;

an additional impedance element having first and second nodes and having a value substantially less than said four impedance elements, said first node of said additional impedance element coupled to said second end of said first impedance pair and said second node of said additional impedance element coupled to said second end of the said second impedance pair, creating a first differential voltage between a first voltage of said first end of said additional impedance element and said first ends of said first and additional impedance pairs and a second differential voltage between a second voltage of the additional node of said second impedance element and said first ends of said first and second impedance pairs;

switching means for alternatively selecting between said first and second differential voltages;

integrating means coupled to said first ends and said switching means and having an output for producing ramped signal having a value representing an integral of said selected differential voltages, said integrating means includes a capacitor which is charged at a rate proportional to said first differential voltage and discharged at a rate proportional to said second differential voltage, said charging occurring during a first time interval and said discharging occurring during a second time interval;

a pulse-forming circuit coupled to said output of said integrating means for forming a series of digital pulses, said digital pulses fed back to control said switching means, wherein said pulse-forming circuit includes level detection means responsive to a predetermined voltage level for alternatively switching between a first and second state when said ramped signal from said integrating means reached said predetermined voltage level;

a clock with a first period;

timing means for adjusting a second period of an output of said detection means and synchronizing means for synchronizing said output of said detection means to said clocks, wherein said timing means comprise a first flip-flop for adjusting the second period to an integer multiple of the first period of said clock and wherein said synchronizing means generates said series of digital pulses having a pulse width corresponding to said discharging interval, said synchronizing means comprising a second flip-flop having an output synchronized to said clock; and

bridge supply switching means respectively coupling said reference voltage and said grounding voltage to said first and second junctions for providing third and fourth differential voltages.