Latch circuit for receiving small amplitude signals

• US 5,877,642 A
• Filed: 11/18/1996
• Issued: 03/02/1999
• Est. Priority Date: 11/17/1995
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Takahashi, Hiroyuki
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ADOLPHE, EUNJA
• Application Number:
  US08/751,612
• Time in Patent Office: 834 Days
• Field of Search: 327/202, 327/203, 327/207, 327/208-212, 327/218, 327/432, 327/433, 327/324, 327/563, 326/66, 326/67, 326/77, 326/69, 326/126, 326/110, 326/109
• US Class Current: 327/207
• CPC Class Codes: H03K 3/021 by the use, as active elements, of more than one type of element or means, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356069 using additional transistors in the feedback circuit H03K3/356104, H03K3/3562 take precedence

Abstract

The latch circuit having an input stage supplied with an input signal and, when activated, producing an output signal responsive to the input signal, and an latching stage coupled to the input stage and, when activated, holding a level of the output signal, the input stage including a pair of bipolar transistors Q1, Q2 coupled in a differential form, the latching stage including a pair of insulated gate field effect transistors M1, M2 coupled in a differential form.

Claims

1. A semiconductor circuit comprising:

a first bipolar transistor connected between a first node and a second node and having a base connected to a first input terminal;

a second bipolar transistor connected between a third node and said second node and having a base connected to a second input terminal;

a first resistive element connected between a first power supply line and said first node;

a second resistive element connected between said first power supply line and said third node;

a first MOS transistor connected between said first node and a fourth node and having a gate;

a second MOS transistor connected between said third node and said fourth node and having a gate;

a first current source connected to said second node and operating during a first period of time;

a second current source connected to said fourth node and operating during a second period of time;

a first signal transfer circuit coupled between said first node and the gate of said second MOS transistor; and

a second signal transfer circuit coupled between said third node and the gate of said first MOS transistor.

2. The circuit as claimed in claim 1, wherein said first signal transfer circuit has a third bipolar transistor connected between said first power supply line and a first output terminal and having a base connected to said first node, and a third MOS transistor connected between said first output terminal and a second supply line and having a gate receiving a bias voltage, and said second signal transfer circuit has a fourth bipolar transistor connected between said first power supply line and a second output terminal and having a base connected to said third node, and a fourth MOS transistor connected between said second output terminal and said second supply line and having a gate receiving said bias voltage.

3. The circuit as claimed in claim 1, wherein said first signal transfer circuit has a third bipolar transistor connected between said first power supply line and a first output terminal and having a base connected to said first node, a third resistive element connected between said first output terminal and a fifth node, a third MOS transistor connected between said fifth node and a second supply line and having a gate receiving a bias voltage, and said second signal transfer circuit has a fourth bipolar transistor connected between said first power supply line and a second output terminal and having a base connected to said third node, a fourth resistive element connected between said second output terminal and a sixth node, a fourth MOS transistor connected between said sixth node and said second supply line and a gate receiving said bias voltage.

4. The circuit as claimed in claim 1, wherein said first current source has a third MOS transistor connected between said second node and a second supply line and having a gate receiving an inverted control signal, said second current source has a fourth MOS transistor connected between said fourth node and said second supply line and having a gate receiving said control signal.

5. The circuit as claimed in claim 1, wherein said first signal transfer circuit has a third MOS transistor of a first conductive type connected between said first power supply line and a fifth node and having a gate connected to said first node, a fourth MOS transistor of a second conductive type connected between said fifth node and a second power supply line and having a gate connected to said fifth node, a fifth MOS transistor of said first conductive type connected between said first power supply line and a first output terminal and having a gate connected to said third node, a sixth MOS transistor of said second conductive type connected between said first output terminal and said second power supply line and having a gate connected to said fifth node, and said second signal transfer circuit has a seventh MOS transistor of said first conductive type connected between said first power supply line and a sixth node and having a gate connected to said third node, an eighth MOS transistor of said second conductive type connected between said sixth node and said second power supply line and having a gate connected to said sixth node, a ninth MOS transistor of said first conductive type connected between said first power supply line and a second output terminal and having a gate connected to said first node, and a tenth MOS transistor connected between said second output terminal and said second power supply line and having a gate connected to said sixth node.