Programmable clock generator

• US 5,877,656 A
• Filed: 05/29/1997
• Issued: 03/02/1999
• Est. Priority Date: 10/30/1995
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mann, Eric N., Torode, John Q.
• Primary Examiner(s): Mis, Davis
• Application Number:
  US08/865,342
• Time in Patent Office: 642 Days
• Field of Search: 331/1 A, 331/2, 331/16, 331/17, 331/18, 331/25, 331/74, 331/108 D, 331/108 C, 327/105, 327/107, 327/147-150, 327/156-159, 455/260
• US Class Current: 331/16
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Claims

1. A circuit for generating a clock signal comprising:

a programmable non-volatile memory for storing bits of configuration information to determine a frequency of oscillation of said clock signal; and

a clock generator receiving said configuration information and generatine said clock signal having said frequency of oscillation,

wherein said programmable non-volatile memory and said clock generator are on a single integrated circuit.

2. The circuit according to claim 1 wherein said clock generator and said plurality of clock generators each comprise a phase-locked-loop.

3. The circuit according to claim 1 wherein said configuration information comprises a set of frequency based configuration bits for determining the frequency at which the clock output will oscillate and a set of general information bits for controlling one or more non-frequency parameters of the circuit.

4. The circuit according to claim 1 wherein said programmable non-volatile memory comprises an EPROM.

5. The circuit according to claim 1 wherein said programmable non-volatile memory comprises a single-poly EPROM.

6. The circuit according to claim 1 wherein said programmable non-volatile memory is programmable after said circuit is packaged.

7. The circuit according to claim 1 wherein said non-volatile memory can be programmed during a wafer sort step of the production process.

8. The circuit according to claim 1 wherein said non-volatile memory can be programmed in the field by the end user of the circuit.

9. The circuit of claim 1, wherein said configuration information also configures at least one member of the group selected from a parameter of said clock generator, an input threshold of said circuit, an output drive level of said circuit, an output multiplexer, and an output divider.

10. The circuit of claim 9, wherein said configuration information further configures two or more members of said group.

11. The circuit of claim 10, wherein said configuration information further configures all of said members of said group.

12. The circuit of claim 1, further comprising a second memory for storing information configuring one or more members of the group selected from a parameter of said clock generator, an input threshold of said circuit, an output drive level of said circuit, an output multiplexer, and an output divider.

13. The circuit of claim 12, wherein said second memory is separate from said programable non-volatile memory.

14. A single integrated circuit for generating a plurality of clock signals each having a a frequency, said single intergrated circuit comprising:

A programmable non-volatile memory for storing bits of configuration information to determine to frequency of each of said clock signals;

an internal or external reference frequency source that generates a reference output signal;

a first clock generator having (a) a set of inputs to receive said configuration information and (b) a reference input coupled to said reference output signal, said first clock generator for generating one of said plurality of clock signals at one of said frequencies determined by said configuration information;

a plurality of fixed frequency clock generators each having (a) a set of inputs to receive said configuration information and (b) a reference input coupled to said reference output signal, each of said plurality of clock generators having an output signal that oscillates at fixed frequency; and

a multiplexer having (i) a plurality of inputs connected to each of the outputs from said first clock generator and said plurality of clock generators and (ii) a bus input connected to said bits of configuration information, said multiplexer for presenting at least one of said clock output signals.

15. The circuit according to claim 14 wherein each of said clock generator and said plurality of clock generators comprises one of a plurality of phase-locked loops.

16. The circuit according to claim 14 wherein said configuration information comprises a set of frequency based configuration bits for determining the frequency at which the fixed frequency clock will oscillate and a set of general information bits for controlling one or more non-frequency parameters of the circuit.

17. The circuit according to claim 14 wherein said multiplexer produces said single output signal in response to said bus input.

18. The circuit according to claim 14 wherein said configuration information responds to a select input connected to a plurality of external inputs, said select input provides external programming for producing a signal on said bus input of said multiplexer for determining which of said plurality of inputs will be produce at said set of output signals.

19. The circuit according to claim 16 wherein said general information bits respond to a select input connected to a plurality of external input selects, said select input provides external programming for producing a signal on said bus input of said multiplexer for determining which of said plurality of inputs will be produce at said set of output signals.

20. The circuit according to claim 14 wherein said non-volatile memory is programmable.

21. The circuit according to claim 20 wherein said programmable non-volatile memory comprises an EPROM.

22. The circuit according to claim 20 wherein said programmable non-volatile memory comprises a single-poly EPROM.

23. The circuit according to claim 20 wherein said programmable non-volatile memory is programmable after said circuit is packaged.

24. The circuit according to claim 20 wherein said non-volatile memory can be programmed during a wafer sort step of the production process.