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Annunciator control circuit

  • US 5,877,678 A
  • Filed: 07/24/1997
  • Issued: 03/02/1999
  • Est. Priority Date: 07/24/1997
  • Status: Expired due to Fees
First Claim
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1. An annunciator control circuit adaptable for responding to a plurality of types of fault indicative inputs, comprising:

  • a signal conditioning circuit portion including an input line and an output line, the signal conditioning circuit portion including switch means adjustable for selectively configuring the signal conditioning circuit portion to receive each of the plurality of types of fault indicative inputs at the input line thereof and to provide a conditioned fault indicative output signal in response thereto at the output line thereof;

    a first latching circuit portion connected to the output line of the signal conditioning circuit portion and having a first output line;

    a first switching transistor including a base, collector, and emitter, the base connected to the first output line of the first latching circuit portion;

    wherein, in response to receipt of the conditioned fault indicative output signal from the signal conditioning circuit portion, an output at the first output line of the first latching circuit portion latches the first switching transistor in an ON state;

    a second latching circuit portion connected to the output line of the signal conditioning circuit portion and having an output line;

    a second switching transistor including a base, collector and emitter, the base connected to the output line of the second latching circuit portion;

    wherein, in response to receipt of the conditioned fault indicative input signal from the signal conditioning circuit portion, an output at the output line of the second latching circuit portion latches the second transistor in an ON state;

    wherein the first latching circuit portion includes a second output line, the annunciator control circuit further comprising;

    a third switching transistor including a base, collector and emitter, the base connected to the second output line of the first latching circuit portion, wherein, in response to receipt of the conditioned fault indicative output signal from the signal conditioning circuit portion, an output at the second output line of the first latching circuit portion latches the third transistor in an OFF state; and

    a fourth switching transistor including a base, collector and emitter, the base connected to the output line of the second latching circuit portion, the third and fourth transistors connected in series, wherein, in response to receipt of the conditioned fault indicative output signal from the signal conditioning circuit portion, the output at the output line of the second latching circuit portion latches the fourth transistor in an ON state.

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