D/A converter with a Gamma correction circuit

• US 5,877,717 A
• Filed: 12/15/1997
• Issued: 03/02/1999
• Est. Priority Date: 12/15/1997
• Status: Expired due to Term

• Current Assignee: Transpacific IP Group Limited
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chang, Chia-Yuan, Rau, Yong-Nian, Tu, Nang-Ping
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/990,443
• Time in Patent Office: 442 Days
• Field of Search: 341/138, 341/144-154
• US Class Current: 341/150
• CPC Class Codes: H03M 1/664 Non-linear conversion not otherwise provided for in subgroups of H03M1/66
• CPC Class Codes: H03M 1/682 both converters being of the unary decoded type
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals

Abstract

A D/A converter with a Gamma correction circuit according to the invention is designed for C-DAC which takes up much less space than the conventional R-DAC and 2-divided C-DAC. Therefore, this D/A converter has advantages of simple design and low cost. Furthermore, users can freely define the shape of a Gamma correction conversion curve to thereby widen application areas by adjusting terminal voltages.

Claims

1. A D/A converter with a Gamma correction circuit, which receives N-bit digital data and then outputs a corresponding analog voltage, comprising:

a plurality of terminal voltage sources;

a terminal voltage selector, the input terminals of which are coupled to said terminal voltage sources;

a first decoder which decodes the k highest bits of said N-bit digital data, thereby controlling said terminal voltage selector to obtain a corresponding first voltage and a second voltage from said terminal voltage sources, wherein the value of said first voltage is less than that of said second voltage;

a second decoder which receives and then decodes a plurality of sets of m-bit digital data in ascending order, wherein said sets of m-bit digital data are obtained by dividing N-k lowest bits of said N-bit digital data;

a voltage-dividing selector which equally divides the voltage difference between said first voltage and said second voltage into 2^m -2 node voltages with values between said first voltage and said second voltage, and then selects and outputs corresponding voltages of said sets of m-bit digital data from said first voltage, said node voltages and said second voltages according to the output controls of said second decoder;

a first switch, a second switch, a third switch and a fourth switch connected to each other in series and coupled between the output of said voltage-dividing selector and ground;

a sixth switch and a fifth switch connected to each other in series and coupled between the output of said voltage-dividing selector and ground;

a first capacitor coupled between the connecting node of said first switch, said second switch, and said ground;

a second capacitor, one terminal of which is connected to the connecting node of said second switch and said third switch, and the other terminal of which is connected to the connecting node of said sixth switch and said fifth switch;

a third capacitor connected in parallel across said fourth switch; and

a fourth capacitor coupled between the output of said voltage-dividing selector and said ground,

wherein the charges of said first capacitor through said fourth capacitor are re-distributed by controlling the operations of said first switch through said sixth switch to combine the corresponding voltages of said sets of m-bit digital data into an analog voltage output from the connecting node of said second capacitor, said second switch and said third switch.

2. A D/A converter as claimed in claim 1, wherein the operations of said first switch through said sixth switch are as follows:

(a) said first switch and said sixth switch are turned off while said second switch and said fifth switch are turned on, thereby discharging said first capacitor through said third capacitor until potentials thereof are the same as that of ground potential, and at this time, the lowest set of m-bit digital data is decoded by said second decoder to cause said voltage-dividing selector to output a corresponding voltage;

(b) said first switch, said fourth switch and said fifth switch are turned on while said second switch, third switch and sixth switch are turned off, thereby charging said first capacitor by the output voltage of said voltage-dividing selector;

(c) said first switch, fourth switch and sixth switch are turned off while said second switch, third switch and fifth switch are turned on, thereby re-distributing the charges stored in the first capacitor with the participation of said second capacitor and third capacitor, and at this moment, the next set of m-bit digital data is decoded by said second decoder to cause said voltage-dividing selector to output a corresponding voltage;

(d) steps (b) and (c) are repeated until the last set (the highest set) of m-bit digital data is completely decoded to cause said voltage-dividing selector to output a corresponding voltage; and

(e) said first switch, said second switch, said third switch and said fifth switch are turned off while said fourth switch and sixth switch are turned on, so that the fourth capacitor is charged by the corresponding voltage of said last set of m-bit digital data, and finally, the voltage value of the second capacitor plus the voltage value of the fourth capacitor is the output voltage of the D/A converter.

3. A D/A converter as claimed in claim 1, wherein the proportion among said first capacitor, second capacitor and third capacitor is 1:

1;

2^m -2.

4. A D/A converter as claimed in claim 1, wherein the number of said terminal voltage sources is 2^k+ 1 which forms 2^k voltages, wherein corresponding voltages are determined from said 2^k voltages by decoding the k highest bits of said N-bit digital data.

5. A D/A converter as claimed in claim 1, wherein the N-k lowest bits of said N-bit digital data are divided into a plurality of sets of m-bit digital data in descending order, and if the last set of m-bit digital data is not sufficient for m bits, the required number of "0s" are added to the right-hand side thereof to completely match the m bits.

6. A D/A converter as claimed in claim 1, wherein said voltage-dividing selector comprises:

a voltage-dividing network consisting of 2^m -1 proportion-equal resistors connected to each other in series, coupled between said first voltage and said second voltage for obtaining 2^m -2 node voltages; and

a selector, the inputs of which are coupled to said first voltage, 2^m -2 node voltages and second voltage, for selecting and then outputting corresponding voltages, according to output controls which are generated by decoding said sets of m-bit digital data by said second decoder.

7. A D/A converter as claimed in claim 1, further comprising:

a timing controller for controlling the operations of said first switch through said sixth switch;

a shift register for storing said N-k bits digital data and outputting said sets of m-bit digital data in ascending order for being decoded by said second decoder; and

a register for storing said k bits digital data and then inputting said k bits digital data to said first decoder.

8. A D/A converter as claimed in claim 1, wherein said N, k and m all are positive integral numbers, wherein N is more than k.

9. A D/A converter as claimed in claim 1, wherein said first switch through said sixth switch can be replaced with MOS transistors.

10. A D/A converter as claimed in claim 1, wherein the set number of said m-bit digital data is (N-k)/m!, wherein (N-k)/m! denotes the smallest number greater than or equal to (N-k)/m.