System and method for implementing an overlay pathway

• US 5,877,741 A
• Filed: 04/19/1996
• Issued: 03/02/1999
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Chee, Lawrence P., Mulvenna, John David
• Primary Examiner(s): Zimmerman, Mark K.
• Assistant Examiner(s): Kovalick, Vincent E.
• Application Number:
  US08/632,543
• Time in Patent Office: 1,047 Days
• Field of Search: 345/113, 345/114, 345/132, 345/523
• US Class Current: 345/629
• CPC Class Codes: G06F 3/1431 using a single graphics controller
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G06F 3/147 using display panels
• CPC Class Codes: G09G 2310/0229 De-interlacing
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/08 Cursor circuits
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence

Abstract

A system and method for processing overlay display data. A display FIFO pipeline processes background graphics display data and a separate overlay FIFO pipeline processes overlay display data stored in an off-screen part of a graphics memory. The overlay FIFO pipeline performs format conversion, interpolation and scaling on the overlay display data and outputs it to an overlay mux. The overlay mux selects between the outputs of the display FIFO pipeline and the overlay FIFO pipeline in the processing of each scan line.

Claims

1. In a computer system having a graphics memory that stores background graphics display data and overlay data, a graphics controller, comprising:

a display FIFO pipeline that reads in the background graphics display data from the graphics memory;

an overlay FIFO pipeline that reads in the overlay display data from said graphics memory, wherein the overlay display data is stored in an off-screen part of the graphics memory in a format native to a source that produces the overlay display data;

an overlay mux that selectively outputs, for a current scan line, one of the background graphics data display and the overlay display data to a display;

a vertical counter;

a vertical display enable unit coupled to said vertical counter, said vertical display enable unit determining whether a subset of overlays are visible on said current scan line;

an overlay select unit coupled to said vertical display enable unit, said overlay select unit determining an order that overlay data for said subset of overlays is written to said overlay FIFO pipeline, said overlay select unit sending memory load, overlay select, and start address signals to said overlay FIFO pipeline; and

a horizontal display enable unit coupled to said overlay select unit, said horizontal display enable unit instructing said overlay FIFO pipeline when to begin processing of said overlay display data.

2. The controller of claim 1, wherein said overlay FIFO pipeline comprises:

a FIFO that receives the overlay display data from said off-screen part of the graphics memory; and

a format converter that converts the overlay display data from said format native to said source that produces the overlay display data into a format capable of being displayed by said display.

3. The controller of claim 2, wherein said overlay FIFO pipeline further comprises a unit coupled to said format converter that scales the overlay display data.

4. The controller of claim 2, wherein said overlay FIFO pipeline further comprises a unit coupled to said format converter that interpolates the overlay display data.

5. The controller of claim 1, further comprising a priority logic unit for arbitrating memory access requests to said graphics memory using a multi-tiered approach, wherein upper tier memory access requests can interrupt existing lower tier memory access requests.

6. A method for processing overlay display data, comprising the steps of:

(1) storing overlay display data in an off-screen part of a graphics memory, wherein said overlay display data is stored in a format native to at least one source;

(2) retrieving, by a display FIFO pipeline, background graphics display data from an on-screen part of said graphics memory;

(3) retrieving, by an overlay FIFO pipeline, overlay display data for a source;

(4) converting, by said overlay FIFO pipeline, said retrieved overlay display data into a format capable of being displayed by a display;

(5) sending, by an overlay mux, one of said background graphics display data and said converted overlay display data to said display;

(6) determining which overlay display data is visible on a current scan line;

(7) determining an order that said overlay FIFO pipeline reads overlay display data out of said graphics memory; and

wherein said step (7) comprises the step of determining said order based upon a relative assignment of registers.

7. A method for processing double buffered overlay display data, comprising the steps of:

(1) alternately storing overlay display data in one of two off-screen parts of a graphics memory, wherein said overlay display data is stored in a format native to a source; and

(2) alternately retrieving, by an overlay FIFO pipeline, said overlay display data from one of said two off-screen parts of said graphics memory, wherein said step of alternately retrieving is based upon a complementary relation of enable bit registers that are associated with said two off-screen parts of said graphics memory.

8. A computer system, comprising:

a microprocessor;

a data bus coupled to said microprocessor

a graphics memory that stores background graphics display data and overlay data, wherein said overlay display data is stored in an off-screen part of said graphics memory in a format native to a source that produces said overlay display data; and

a graphics controller coupled to said data bus, said graphics controller comprising;

a display FIFO pipeline that reads in said background graphics display data from said graphics memory;

an overly FIFO pipeline that reads in said overlay display data from said graphics memory; and

an overlay mux that selectively outputs, for a current scan line, one of said background graphics display data and said overlay display data to be used by a display; and

a control unit, said control unit comprising;

a vertical display enable unit coupled to said vertical counter, said vertical display enable unit determining whether a subset of overlays are visible on said current scan line;

an overlay select unit coupled to said vertical display enable unit, said overlay select unit determining an order that overlay data for said subset of overlays is written to said overlay FIFO pipeline, said overlay select unit sending memory load, overlay select, and start address signals to said overlay FIFO pipeline; and

a horizontal display enable unit coupled to said overlay select unit, said horizontal display enable unit instructing said overlay FIFO pipeline when to begin processing of said overlay display data.

9. The computer system of claim 8, wherein said overlay FIFO pipeline comprises:

a FIFO that receives the overlay display data from said off-screen part of the graphics memory; and

a format converter that converts the overlay display data from said format native to said source that produces the overlay display data into a format capable of being displayed by said display.

10. The computer system of claim 9, wherein said overlay FIFO pipeline further comprises a unit coupled to said format converter that scales the overlay display data.

11. The computer system of claim 9, wherein said overlay FIFO pipeline frtther comprises a unit coupled to said format converter that interpolates the overlay display data.

12. The computer system of claim 8, further comprising a priority logic unit for arbitrating memory access requests to said graphics memory using a multi-tiered approach, wherein upper tier memory access requests can interrupt existing lower tier memory access requests.

13. The computer system of claim 8, wherein said overlay mux outputs display data to a TV converter, said TV converter coupled to said display.

14. The computer system of claim 8, wherein said overlay mux outputs display data to a LCD interface, said LCD interface coupled to said display.

15. The computer system of claim 8, wherein said overlay mux outputs display data to a digital-to-analog converter, said digital-to-analog converter coupled to said display.