Multi-state Flash EEprom system on a card that includes defective cell substitution

• US 5,877,986 A
• Filed: 12/29/1997
• Issued: 03/02/1999
• Est. Priority Date: 04/13/1989
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/999,472
• Time in Patent Office: 428 Days
• Field of Search: 365/185.09, 365/185.29, 365/185.33, 365/218, 371/21.6, 371/40.1
• US Class Current: 365/185.33
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A memory card connectable to a computer system, comprising:

an array of Electrically Erasable and Programmable Read Only Memory ("EEPROM") cells partitioned into a plurality of flash sectors, the cells of the array being individually programmable into more than two states in order to store more than one bit of data per cell;

each flash sector being a group of cells that are erasable together as a unit, and having a portion thereof reserved as redundant cells; and

a memory controller for controlling operations of the EEPROM cells;

error detection means within said memory controller for detecting any defective cells within the array;

defect pointers, each generated by said memory controller for linking a detected defective cell'"'"'s address to that of a corresponding redundant cell substituting for the defective cell, said defect pointers being stored within the array; and

defective cell substituting means within said memory controller and responsive to said defect pointers for substituting said detected defective cell with said corresponding redundant cells.

2. The memory card as in claim 1, wherein said plurality of sectors have a portion thereof reserved as redundant sectors, and said EEPROM controller, upon detecting more than a predetermined number of defective cells in a sector, substitutes said sector with one of said redundant sectors.

3. The memory card as in claim 2, wherein said EEPROM controller including a circuit for implementing error correction codes for detecting and correcting errors in the operations of the EEPROM cells.

4. The memory card as in claim 1, wherein said memory card is compatible with a magnetic disk drive storage system and capable of substituting therefor in said computer system.

5. A memory card connectable to a computer system, said memory card comprising:

an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, the individual sectors including a user data portion and a spare portion of the group of memory cells, the cells of the array being individually programmable into more than two states in order to store more than one bit of data per cell,

a memory controller for controlling operation of the memory cell array and interfacing the memory cell array with the computer system,

means within said memory controller for identifying defective cells within the user data portion of individual ones of said plurality of sectors, and

means including said memory controller and responsive to detection of a defective cell within the user data portion of one of said plurality of sectors for substituting therefore a corresponding redundant cell within the spare portion of said one of said plurality of sectors.

6. The memory card of claim 5, which additionally comprises means within said memory controller for, upon detecting a defective sector having more than a predetermined number of defective cells therein, substituting another of said plurality of sectors for the defective sector.

7. The memory card of claim 5, which additionally comprises means within said memory controller for storing and accessing error correction codes in the spare portions of the sectors which are related to data stored in the user data portions of the same sectors.

8. The memory card of claim 5, wherein said memory card is compatible with a magnetic disk drive storage system and capable of being substituted therefor in said computer system.

9. A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising:

providing said memory array and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system,

programming the individual cells of the array into one of more than two programmable states in order to store more than one bit of data per cell,

reserving a portion of the memory cells within the individual sectors as spare cells, remaining cells of the individual sectors being designated for storing data,

enabling the controller to detect when a cell within the data portion of a sector becomes defective,

causing the controller to store an address of such a detected defective cell, and

thereafter causing the controller to substitute for the defective cell a redundant cell from the spare cells of the sector in which the defective cell is detected.

10. The method according to claim 9, wherein the storage of an address of a detected defective cell includes storing the address of the detected defective cell within the spare cells of the sector in which the defective cell exists.

11. The method according to claim 10, wherein detecting the address of a defective cell includes maintaining a defect map which links addresses of defective cells to substitute redundant cells.

12. The method according to claim 11, wherein detecting the address of a defective cell includes storing the defect map in the memory array.

13. The method according to claim 9, additionally comprising:

reserving a number of the sectors as redundant sectors,

in response to a number of occurrences of a defective cell being detected within a single sector exceeding a predetermined number, marking such a single sector as a defective sector, and

thereafter remapping the defective sector into one of the redundant sectors as a substitute for the defective sector.

14. The method according to claim 13, wherein the marking of a sector as the defective sector includes placing an address of the defective sector into a defect map that includes an address of the substitute redundant sector, thereby causing the redundant sector to be accessed in response to a request to access the defective sector.

15. The method according to claim 13, wherein a defect map is stored in the memory cell array.

16. The method according to claim 13, wherein the marking and remapping operations are under the control of said memory controller.

17. The method according to claim 9, additionally comprising storing addresses of the sectors in the spare cells of the sectors to which the address pertains.

18. The method according to claim 9, additionally comprising storing in the spare cells of the individual sectors an error correction code for data stored in corresponding ones of the sectors.