Digital variable symbol timing recovery system for QAM

• US 5,878,088 A
• Filed: 04/10/1997
• Issued: 03/02/1999
• Est. Priority Date: 04/10/1997
• Status: Expired due to Term

• Current Assignee: Thomson Licensing Dtv
• Original Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Inventors: Ramaswamy, Kumar, McNeely, David Lowell, Knutson, Paul Gothard
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Maddox, Michael W.
• Application Number:
  US08/835,915
• Time in Patent Office: 691 Days
• Field of Search: 375/324, 375/327, 375/320, 375/354, 375/355, 375/371, 375/373, 375/376, 375/260, 375/261, 375/268, 375/269, 375/326, 329/304, 329/306, 329/307, 329/308, 329/347, 329/348, 329/363
• US Class Current: 375/324
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/0335 Gardner detector

Abstract

A receiver is arranged for receiving a transmitted quadrature amplitude modulated (QAM) signal representing successive symbols, and including an in-phase (I) component and a quadrature (Q) component. In such a receiver, a timing recovery system includes a source of samples representing the QAM signal produced at a fixed frequency. A first chain of processing circuitry for the I component includes a first demodulator, coupled to the sample source, for demodulating the I component of the QAM signal to baseband; and a first interpolator, coupled to the first demodulator and responsive to a control signal, for producing I component samples taken at times synchronized to the transmitted symbols. A second chain of processing circuitry for the Q component includes a second demodulator, also coupled to the sample source, for demodulating the Q component of the QAM signal to baseband; and a second interpolator, coupled to the second demodulator and responsive to a control signal, for producing Q component samples taken at times synchronized to the transmitted symbols. A phase error detector is coupled to the first and the second interpolators, and detects the phase error between the sample times of the I and Q component samples from the first and second interpolators and times of the successive transmitter symbols. A summer is coupled to the phase error detector and a source of a nominal delay signal. A numerically controlled delay circuit, is coupled to the summer, for producing the respective control signals for the first and second interpolators.

Claims

1. In a receiver receiving a transmitted quadrature amplitude modulated (QAM) signal representing successive symbols, the QAM signal including an in-phase (I) component and a quadrature component (Q), a timing recovery system comprising:

a source of samples representing the QAM signal at a fixed frequency;

processing circuitry for the I component, comprising;

a first demodulator, coupled to the sample source, for demodulating the I component of the QAM signal to baseband; and

a first interpolator, coupled to the first demodulator and responsive to a control signal, for producing I component samples taken at times synchronized to the transmitted symbols;

processing circuitry for the Q component, comprising;

a second demodulator, coupled to the sample source, for demodulating the Q component of the QAM signal to baseband; and

a second interpolator, coupled to the second demodulator and responsive to a control signal, for producing Q component samples taken at times synchronized to the transmitted symbols;

a phase error detector, coupled to the first and the second interpolators, for detecting a phase error between the sample times of the transmitter synchronized I and Q samples respectively produced by the first and second interpolators and times of the successive transmitter symbols;

a source of a nominal delay signal;

a summer coupled to the phase error detector and the nominal delay signal source; and

a numerically controlled delay circuit, coupled to the summer, for producing the respective control signals coupled to the first and second interpolators.

2. The system of claim 1 further comprising:

a source of a Q component timing correction signal; and

a second summer, coupled to the Q component timing correction signal source and between the numerically controlled delay circuit and the second interpolator.

3. The system of claim 1, wherein:

the first demodulator is a +1, 0, -1, 0 demodulator;

the I component processing circuitry further comprises a first decimator, coupled between the first demodulator and the first interpolator, for producing baseband I component samples;

the second demodulator is a +1, 0, -1, 0 demodulator; and

the Q component processing circuitry further comprises a second decimator, coupled between the second demodulator and the second interpolator, for producing baseband Q component samples.

4. The system of claim 3, wherein:

the sample source comprises;

an analog-to-digital converter, responsive to the received QAM signal and a clock signal, for generating the QAM signal representative samples; and

a clock signal generator generating the clock signal at a frequency of at least four times the transmitted symbol frequency;

the system further comprises;

a modulo-four counter, coupled to the clock signal generator and having an output terminal producing a signal having a value which is one of 1, 2, 3 and 4;

a first gating circuit, coupled to the modulo-four counter, for producing a gating signal when the value of the signal at the output terminal of the modulo-four counter signal is one of `1` and `3`;

a second gating circuit, coupled to the modulo-four canter, for producing a gating signal when the value of the counter signal is one of `2` and `4`;

the first decimator comprises a first delay circuit, having a clock input terminal coupled to the clock signal generator, and an enable input terminal coupled to the second gating circuit; and

the second decimator comprises;

a second delay circuit, having a clock input terminal coupled to the clock signal generator, and an enable input terminal coupled to the first gating circuit; and

a third delay circuit, having a clock input terminal coupled to the clock signal generator, and an enable input terminal coupled to the second gating circuit.

5. The system of claim 4, wherein:

the first +1, 0 -1, 0 demodulator comprises;

a first four-input multiplexer, having respective data input terminals coupled to respective signal sources having values of 0, +1, 0 and -1 and a control input terminal coupled to the modulo-four counter; and

a first multiplier, coupled to the analog-to-digital converter and the first four-input multiplexer, for producing demodulated I component samples; and

the second +1, 0 -1, 0 demodulator comprises;

a second four input multiplexer, having respective data input terminals coupled to respective signal sources having values -1, 0, +1, and 0 and a control input terminal coupled to the modulo-four counter; and

a second multiplier, coupled to the analog-to-digital converter and the second four-input multiplexer, for producing demodulator Q component sample.

6. The system of claim 3, wherein:

the sample source comprises;

an analog-to-digital converter, responsive to the received QAM signal, and a clock signal, for generating the QAM signal representative samples; and

a clock signal generator generating the clock signal at a frequency of at least four times the transmitted symbol frequency;

the system further comprises a modulo-four counter, coupled to the clock signal generator;

the first +1, 0 -1, 0 demodulator comprises;

a first four-input multiplexer, having respective data input terminals coupled to respective signal sources having values of 0, +1, 0 and -1 and a control input terminal coupled to the modulo-four counter; and

a first multiplier, coupled to the analog-to-digital converter and the first four-input multiplexer, for producing demodulated I component samples; and

the second +1, 0 -1, 0 demodulator comprises;

a second four input multiplexer, having respective data input terminals coupled to respective signal sources having values -1, 0, +1, and 0 and a control input terminal coupled to the modulo-four counter; and

a second multiplier, coupled to the analog-to-digital converter and the second four-input multiplexer, for producing demodulator Q component samples.

7. In a receiver receiving a transmitted quadrature amplitude modulated (QAM) signal representing successive symbols, the QAM signal including an in-phase (I) component and a quadrature component (Q) modulated on a QAM subcarrier, a timing recovery system comprising:

a source of samples representing the QAM signal at a fixed frequency;

an interpolator, coupled to the sample source, and responsive to a control signal, for producing QAM samples taken at times synchronized to the QAM subcarrier;

a first demodulator, coupled to the interpolator, for demodulating the I component of the QAM signal to baseband;

a second demodulator, coupled to the interpolator, for demodulating the Q component of the QAM signal to baseband;

a phase error detector, coupled to the first and the second demodulators, for detecting a phase error between the sample times of the transmitter synchronized I and Q samples respectively produced by the first and second demodulators and times of the successive transmitter symbols;

a source of a nominal delay signal;

a summer coupled to the phase error detector and the nominal delay signal source; and

a numerically controlled delay circuit, coupled to the summer, for producing the control signal coupled to the interpolator.

8. The system of claim 7, further comprising:

a first decimator, coupled to the first demodulator, for producing baseband I component samples; and

a second decimator, coupled to the second demodulator, for producing baseband Q component samples;

wherein;

the first demodulator is a +1, 0, -1, 0 demodulator; and

the second demodulator is a +1, 0, -1, 0 demodulator.

9. The system of claim 8, further comprising:

a modulo-four counter, synchronized to the QAM subcarrier synchronized samples from the interpolator, and having, an output terminal producing a signal having a value which is one of 1, 2, 3 and 4;

a first gating circuit, coupled to the modulo-four counter, for producing a gating signal when the value of the signal at the output terminal of the modulo-four counter signal is one of `1` and `3`;

a second gating circuit, coupled to the modulo-four canter, for producing a gating signal when the value of the counter signal is one of `2` and `4`;

wherein;

the first decimator comprises a first delay circuit, having a clock input terminal coupled to the second gating circuit; and

the second decimator comprises;

a second delay circuit, having a clock input terminal coupled to the first gating circuit; and

a third delay circuit, having a clock input terminal coupled to the second gating circuit.

10. The system of claim 9, wherein:

the first +1, 0 -1, 0 demodulator comprises;

a first four-input multiplexer, having respective data input terminals coupled to respective signal sources having values of 0, +1, 0 and -1 and a control input terminal coupled to the modulo-four counter; and

a first multiplier, coupled to the interpolator and the first four-input multiplexer, for producing demodulated I component samples; and

the second +1, 0 -1, 0 demodulator comprises;

a second four input multiplexer, having respective data input terminals coupled to respective signal sources having values -1, 0, +1, and 0 and a control input terminal coupled to the modulo-four counter; and

a second multiplier, coupled to the interpolator and the second four-input multiplexer, for producing demodulator Q component sample.

11. The system of claim 8, further comprising:

a modulo-four counter, synchronized to the QAM subcarrier synchronized samples from the interpolator;

wherein;

the first +1, 0 -1, 0 demodulator comprises;

a first four-input multiplexer, having respective data input terminals coupled to respective signal sources having values of 0, +1, 0 and -1 and a control input terminal coupled to the modulo-four counter; and

a first multiplier, coupled to the interpolator and the first four-input multiplexer, for producing demodulated I component samples; and

the second +1, 0 -1, 0 demodulator comprises;

a second four input multiplexer, having respective data input terminals coupled to respective signal sources having values -1, 0, +1, and 0 and a control input terminal coupled to the modulo-four counter; and

a second multiplier, coupled to the interpolator and the second four-input multiplexer, for producing demodulator Q component samples.