Digital filter having phase-adjustment ability

• US 5,878,096 A
• Filed: 03/24/1997
• Issued: 03/02/1999
• Est. Priority Date: 03/24/1997
• Status: Expired due to Fees

• Current Assignee: Holtek Semiconductor Incorporated
• Original Assignee: Holtek Microelectronics, Inc. (United Microelectronics Corporation)
• Inventors: Shao, Hsuan Ming, Chen, Yi Ren
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Roundtree, Joseph
• Application Number:
  US08/826,066
• Time in Patent Office: 708 Days
• Field of Search: 327/90, 327/98, 327/276-278, 327/284, 327/403, 375/340, 375/371, 375/350, 329/303, 329/307, 329/360
• US Class Current: 375/371
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

Disclosed is a digital filter having phase-adjustment ability, and more particularly to a digital filter system which can restore the phase of data transmitted via digital radio communication and thereby enhances the noise-immunity of data and the correct bit decision. The digital filter mainly includes a hold back data unit, a digital filter unit, and a signal phase modify unit to remove noises in the signals and to modify and restore correct digital wave-form signals. The digital filter having phase-adjustment ability is suitable for use in digital radio phones, pagers, etc. commonly found in the radio communication systems.

Claims

1. A digital filter having phase-adjustment ability, comprising:

a hold back data unit including a group of series-connected registers;

a first of said registers having a data input end for receiving data input signals, and others of said registers each having a data input end connected to a data output end of a preceding register;

each of said registers having an enable input end which inputs a clock signal having a frequency more than eight times a frequency of said data input signals;

a last one of these registers having a data output end from where a hold back data signal is output;

a digital filter unit connected to said data output end of said last register of said hold back data unit, said digital filter unit comprising;

a threshold frequency counter which has an input end for inputting a data input signal and a hold back data signal for an up or down count decision and then outputting an up or a down count signal;

several cascade half adders, wherein a half adder thereof at a first cascade has an up input end for receiving said up count signal and a down input end for receiving said down count signal, and other half adders at a second and subsequent cascades all have an up input end connected to an up output end of a preceding half adder and a down input end connected to a down output end of a preceding half adder with said up and said down output ends of a last half adder of said cascade half adders left unused, and a sample signal of each said cascade is output from said output end of each said half adder of said cascade;

a sample output logic circuit having an input side for receiving sample signals output by said cascade half adders and a feedback signal to generate and output logic decision signals;

a first flip-flop having an input end for receiving said logic decision signals output by said sample output logic circuit, so that a digital data signal is output from a forward output end of said first flip-flop, and a feedback signal is generated by a backward output end of said first flip-flop and sent back to said sample output logic circuit; and

a second flip-flop having an input end connected to said forward output end of said first flip-flop, so that said second flip-flop generates and outputs a digital data signal having a delay of one clock cycle relative to than said digital data signal output by said first flip-flop; and

a signal phase modify unit connected to said digital filter unit for restoring a correct phase of said data signals.

2. A digital filter having phase-adjustment ability as claimed in claim 1, wherein said signal phase modify unit comprises:

a clock counter including several cascade-connected adders, said cascade adders all having a carry output end connected to an input end of a next cascade adder, and said clock counter outputting a group of clock count value signals;

a phase arbitration circuit which compares clock count values produced by said clock counter with said digital data signals generated by said first and said second flip-flop and then outputs an edge signal for said digital data signals and a read enable clock delay or exceed state signal; and

an adjust logic implement which is a logic circuit to process said clock count value signals, said edge signal for said digital data signals, said read enable clock delay or exceed state signal, and a lock state signal sent thereto, so as to generate multiple cascade fine or coarse adjustment feedback signals to modify and restore the phase of said data signals received by said digital filter.

3. A digital filter having phase-adjustment ability as claimed in claim 2, wherein said adjust logic implement further comprising:

a state decision logic circuit having an input side for inputting an X times frequency clock signal, digital data signals, and a lock state signal, as well as said edge signal output by said phase arbitration circuit, said state decision logic circuit making logic decision and outputting several pairs of output signals;

an adjust state logic implement including several cascade-connected flip-flop and logic gates, each of said cascade flip-flop having an input end connected to an OR gate and an NAND gate and then connected to one pair of output signals having been logically decided and output by said state decision logic circuit;

each of said cascade flip-flop having a forward output end for outputting an adjust state signal for the same cascade, and a backward output end for outputting a feedback signal to said input end thereof;

a state logic circuit having an input side connected to said adjust state signals output by said several cascade flip-flop;

said state logic circuit making logic decision on said input adjust state signals and then generating at an output end an adjust state trigger signal which is sent back to said input side of said state decision logic circuit; and

an adjust decision logic circuit having an input side to input an X times frequency clock signal, an adjust state trigger signal, and said read enabale clock delay or exceed state signal output by said phase arbitration circuit;

said adjust decision logic circuit adjusting all these input signals and outputting from a first adjust output end a delay adjust signal to said input end of said first cascade adder of said clock counter and from a second adjsut output end an exceed adjust signal to said input end of said second cascade adder of said clock counter, forming a feedback, adjustment, and control of signals.