Digital filter having phase-adjustment ability
First Claim
Patent Images
1. A digital filter having phase-adjustment ability, comprising:
- a hold back data unit including a group of series-connected registers;
a first of said registers having a data input end for receiving data input signals, and others of said registers each having a data input end connected to a data output end of a preceding register;
each of said registers having an enable input end which inputs a clock signal having a frequency more than eight times a frequency of said data input signals;
a last one of these registers having a data output end from where a hold back data signal is output;
a digital filter unit connected to said data output end of said last register of said hold back data unit, said digital filter unit comprising;
a threshold frequency counter which has an input end for inputting a data input signal and a hold back data signal for an up or down count decision and then outputting an up or a down count signal;
several cascade half adders, wherein a half adder thereof at a first cascade has an up input end for receiving said up count signal and a down input end for receiving said down count signal, and other half adders at a second and subsequent cascades all have an up input end connected to an up output end of a preceding half adder and a down input end connected to a down output end of a preceding half adder with said up and said down output ends of a last half adder of said cascade half adders left unused, and a sample signal of each said cascade is output from said output end of each said half adder of said cascade;
a sample output logic circuit having an input side for receiving sample signals output by said cascade half adders and a feedback signal to generate and output logic decision signals;
a first flip-flop having an input end for receiving said logic decision signals output by said sample output logic circuit, so that a digital data signal is output from a forward output end of said first flip-flop, and a feedback signal is generated by a backward output end of said first flip-flop and sent back to said sample output logic circuit; and
a second flip-flop having an input end connected to said forward output end of said first flip-flop, so that said second flip-flop generates and outputs a digital data signal having a delay of one clock cycle relative to than said digital data signal output by said first flip-flop; and
a signal phase modify unit connected to said digital filter unit for restoring a correct phase of said data signals.
3 Assignments
0 Petitions
Accused Products
Abstract
Disclosed is a digital filter having phase-adjustment ability, and more particularly to a digital filter system which can restore the phase of data transmitted via digital radio communication and thereby enhances the noise-immunity of data and the correct bit decision. The digital filter mainly includes a hold back data unit, a digital filter unit, and a signal phase modify unit to remove noises in the signals and to modify and restore correct digital wave-form signals. The digital filter having phase-adjustment ability is suitable for use in digital radio phones, pagers, etc. commonly found in the radio communication systems.
27 Citations
3 Claims
-
1. A digital filter having phase-adjustment ability, comprising:
-
a hold back data unit including a group of series-connected registers;
a first of said registers having a data input end for receiving data input signals, and others of said registers each having a data input end connected to a data output end of a preceding register;
each of said registers having an enable input end which inputs a clock signal having a frequency more than eight times a frequency of said data input signals;
a last one of these registers having a data output end from where a hold back data signal is output;a digital filter unit connected to said data output end of said last register of said hold back data unit, said digital filter unit comprising; a threshold frequency counter which has an input end for inputting a data input signal and a hold back data signal for an up or down count decision and then outputting an up or a down count signal; several cascade half adders, wherein a half adder thereof at a first cascade has an up input end for receiving said up count signal and a down input end for receiving said down count signal, and other half adders at a second and subsequent cascades all have an up input end connected to an up output end of a preceding half adder and a down input end connected to a down output end of a preceding half adder with said up and said down output ends of a last half adder of said cascade half adders left unused, and a sample signal of each said cascade is output from said output end of each said half adder of said cascade; a sample output logic circuit having an input side for receiving sample signals output by said cascade half adders and a feedback signal to generate and output logic decision signals; a first flip-flop having an input end for receiving said logic decision signals output by said sample output logic circuit, so that a digital data signal is output from a forward output end of said first flip-flop, and a feedback signal is generated by a backward output end of said first flip-flop and sent back to said sample output logic circuit; and a second flip-flop having an input end connected to said forward output end of said first flip-flop, so that said second flip-flop generates and outputs a digital data signal having a delay of one clock cycle relative to than said digital data signal output by said first flip-flop; and a signal phase modify unit connected to said digital filter unit for restoring a correct phase of said data signals. - View Dependent Claims (2, 3)
-
Specification