Signal processing delay circuit

• US 5,878,097 A
• Filed: 05/30/1997
• Issued: 03/02/1999
• Est. Priority Date: 04/26/1994
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kimura, Hiroshi, Nara, Takashi, Watanabe, Kunio, Horita, Ryutaro, Ishida, Yoshiteru, Hase, Kenichi
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GHAYOUR, MOHAMMAD H
• Application Number:
  US08/865,704
• Time in Patent Office: 641 Days
• Field of Search: 375/371, 370/516, 370/517
• US Class Current: 375/371
• CPC Class Codes: G11B 20/10 Digital recording or reproducing
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.

Claims

1. A data acquisition circuit for acquiring sampled data in response to a sampling clock signal synchronized with input data thereto, comprising a phase adjustment circuit for achieving a phase adjustment of the sampled data, wherein the phase adjustment circuit includes a signal processing delay circuit including first delay means including first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.

2. A data acquisition circuit according to claim 1, further including means for creating a sampling clock signal synchronized with the input data.

3. A signal recording and reproducing system, comprising:

a recording medium;

a sensor for recording a signal on the recording medium or reproducing a signal from the recording medium;

a signal processing circuit for processing a record signal to the sensor or a reproduction signal therefrom;

an interface circuit for communicating as data items the processed record and reproduction signals;

a processor for controlling operation of the system;

a data acquisition circuit for acquiring sampled data in response to a sampling clock signal synchronized with input data thereto, the data acquisition circuit comprising a phase adjustment circuit for achieving a phase adjustment of the sampled data;

the phase adjustment circuit including a signal processing delay circuit including first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means; and

/or

a data write circuit for writing data on a recording medium, the data write circuit including a write pre-compensation circuit for conducting a positional compensation of data according to a data pattern of the data, the write pre-compensation circuit including a signal processing delay circuit including first delay means including a first analog variable delay circuit of which an amount of delay is controlled according to an external reference signal, the first delay means generating a delay amount control signal and second delay means including a second analog variable delay circuit in which an amount of delay of an input signal thereto is controlled according to the delay amount control signal generated by the first delay means.