Device access controller for virtual video/keyboard/mouse input/output for remote system management and maintenance

• US 5,878,248 A
• Filed: 06/11/1996
• Issued: 03/02/1999
• Est. Priority Date: 06/11/1996
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Shapiro, Jonathan, Linton, Paul D., Tehranian, Michael, Gringorten, Sheldon P., Giancioppo, Michael, Martin, Brian
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/661,571
• Time in Patent Office: 994 Days
• Field of Search: 395/501-504, 395/509, 395/511, 395/515, 395/516, 395/520, 395/526, 395/200.01, 395/200.05, 395/200.09, 395/200.11, 395/200.2, 395/306, 395/280 , 395/308
• US Class Current: 345/502
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
• CPC Class Codes: G06F 3/1454 involving copying of the display data of a local workstation or window to a remote workstation or window so that an actual copy of the data is displayed simultaneously on two or more displays, e.g. teledisplay

Abstract

A device access controller residing in a first computer system for transferring virtual inputs and outputs representing operations of the first system between the first system and a second system. The device access controller includes a video controller for performing video display operations, a video memory for storing video data representing operations of the first system, a network controller for transferring information between the first system and the second system, a controller processor, and a device access controller bus interconnecting the video controller, the network controller and the processor. A video interface is connected between the first system bus and the device access controller bus for receiving video information including video data and video write addresses from the first system bus and into the video memory and controller and the controller processor and network controller are responsive to the writing of video data into the video memory for reading the video information including the video data from the video memory and the video data write addresses from the video controller registers and transmitting the video information including the video data and the video data write addresses to the second system. The device access controller further includes a keyboard interface, a disk interface, and a serial interface operating in manners generally analogous to the video interface for corresponding communicating corresponding data between the first and second systems.

Claims

1. In a first computer system including a processor for performing operations on data and a memory for storing the data, the results of operations on the data and programs for directing the operations of the processor, and a first system bus interconnecting the processor and the memory for transferring data and program instructions therebetween, a device access controller for transferring virtual inputs and outputs representing operations of the first system between the first system and a second system, the device access controller comprising:

a video controller for performing video display operations,

a video memory connected from the video controller for storing video data representing operations of the first system,

a network controller connected to the second system by a network for transferring information between the first system and the second system,

a controller processor for controlling operations of the device access controller,

a device access controller bus interconnecting the video controller, the network controller and the processor, and

a video interface connected between the first system bus and the device access controller bus and responsive to a first system video data write operation on the first system bus for receiving video information including video data and video write addresses from the first system bus and indicating the first system video write operation to the controller processor,

the controller processor being responsive to the indication of the first system video write operation for directing the video controller to write the received video data write addresses into video controller registers and the video data into the video memory at the video write addresses, and

the network controller being responsive to the writing of video data into the video memory for reading the video information including the video data from the video memory and the video data write addresses from the video controller registers and transmitting the video information including the video data and the video data write addresses to the second system.

2. The device access controller of claim 1, wherein:

the video interface is responsive to a first system video data read operation on the first system bus for receiving video information including the video data read addresses from the first system bus and indicating the first system video data read operation to the controller processor,

the controller processor being responsive to the indication of the first system video data read operation for directing the video controller to write the received video data read addresses into the video controller registers, and

the network controller being responsive to the writing of video data read addresses into the video controller registers for reading the video information including the data read addresses from the video controller registers and transmitting the video information including the video data read addresses to the second system.

3. The device access controller of claim 1 wherein the network controller transmits information to the second system in network packets.

4. The device access controller of claim 3, further comprising:

a device access controller memory connected from the device access controller bus, wherein

the network controller reads the video information into the device access controller memory, formats the video information in the device access controller memory into network packets stored therein, and transmits the network packets to the second system.

5. The device access controller of claim 1, further comprising:

a keyboard interface connected to the device access controller bus and to a keyboard controller of the first system,

wherein the network controller is responsive to keyboard information received from the second system for indicating to the controller processor the receipt of information from the second system,

the controller processor is responsive to the received keyboard information for directing the network controller to write the keyboard information to the keyboard interface, and

the keyboard interface is responsive to the keyboard information received from the network controller for providing the keyboard information to the keyboard controller of the first system to appear as keyboard information received directly by the first system from a local keyboard.

6. The device access controller of claim 5, further comprising:

an address mapping interface connected between the controller processor and the keyboard interface for mapping between first system addresses appearing on the first system bus and device access controller bus addresses.

7. The device access controller of claim 1, further comprising:

a disk interface connected between the first system bus and the device access controller bus and responsive to a first system disk write operation on the first system bus for receiving first disk information including disk data and disk write addresses from the first system bus and indicating the first system disk write operation to the controller processor,

the controller processor being responsive to the indication of the first system disk write operation for

writing the first disk information into a device access controller memory, and

directing the network controller to read the first disk information from the device access controller memory and transmit the first disk information to the second system.

8. The device access controller of claim 7, wherein:

the disk interface is responsive to a first system disk read operation on the first system bus for receiving second disk information including disk read addresses from the first system bus and indicating the first system disk read operation to the controller processor,

the controller processor is responsive to the indication of the first system disk read operation for

writing the second disk information into a device access controller memory, and

directing the network controller to read the second disk information from the device access controller memory and transmit the second disk information to the second system,

the second system is responsive to the disk read addresses for transmitting third disk information including the disk data corresponding to the disk read addresses to the network controller,

the network controller is responsive to the third disk information received from the second system for indicating the receipt of the third disk information,

the controller processor is responsive to the indication of receipt of the third disk information for

directing the network controller to provide the third disk information to the disk interface and

directing the disk interface to provide the third disk information to the first system.

9. The device access controller of claim 7, further comprising:

an address mapping interface connected between the controller processor and the disk interface for mapping between first system addresses appearing on the first system bus and device access controller bus addresses.

10. The device access controller of claim 1, further comprising:

an address mapping interface connected between the controller processor and the video interface for mapping between first system addresses appearing on the first system bus and device access controller bus addresses.

11. The device access controller of claim 1, further comprising:

an interrupt mapping interface connected between the controller processor and the first system bus for mapping between interrupts appearing on the first system bus and the device access controller bus.