Power sequence controller with wakeup logic for enabling a wakeup interrupt handler procedure

• US 5,878,264 A
• Filed: 07/17/1997
• Issued: 03/02/1999
• Est. Priority Date: 07/17/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Ebrahim, Zahir
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Kim, Harold J.
• Application Number:
  US08/895,947
• Time in Patent Office: 593 Days
• Field of Search: 395/750.05, 395/750.07, 395/750.01-750.08, 395/182.22
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

A power sequence controller contains wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller. The wakeup logic compares the intercepted wakeup event signal with a wakeup filter mask to determine if the wakeup event signal should be processed or ignored. If the wakeup event signal requires processing, the wakeup logic transitions the system'"'"'s processor to a working state. The wakeup logic also determines if the intercepted wakeup event signal requires software processing. If so, a non-zero value associated with the wakeup event signal is stored in an interrupt source register, which causes the processor to execute an interrupt handler procedure and process the wakeup event signal when it transitions to a working state. The wakeup logic also evaluates the processor sleep state to determine if transitioning the processor from the sleep state to a working state requires execution of a processor wakeup procedure to return the processor to normal operation. In addition, the wakeup logic evaluates the processor sleep state to determine whether transitioning the processor from the sleep state to a working state requires sending a processor reset signal to processor, where the reset signal causes the processor to perform a warm or cold boot procedure, depending on the processor'"'"'s sleep state.

Claims

1. A power sequence controller for use in a device having a processor for executing instructions in an instruction stream, comprising:

a first wakeup mask for storing a mask value indicating which of a predefined set of wakeup event signals are to be ignored and which require transitioning the processor from a sleep state to a working state;

a second wakeup mask for storing a mask value indicating which of the predefined set of wakeup event signals require software processing;

wakeup logic for comparing a wakeup event signal intercepted by the power sequence controller with the first wakeup mask and for generating a processor wakeup signal when the comparison indicates that the intercepted wakeup event signal requires transitioning the processor to the working state; and

wakeup interrupt logic for determining whether the intercepted wakeup event signal requires software processing, and for storing a non-zero value associated with the wakeup event signal in an interrupt source register when the determination indicates that software processing is required;

wherein

the wakeup interrupt logic compares the intercepted wakeup event signal with the second wakeup mask to determine whether the intercepted wakeup event signal requires software processing;

the non-zero value in the interrupt source causes the processor to execute an interrupt handler procedure and process the intercepted wakeup event; and

when the wakeup logic generates a processor wakeup signal in response to the intercepted wakeup event signal and the wakeup interrupt logic determines that the intercepted wakeup event does not require software processing, the wakeup logic transitions the processor to a working state so as to resume execution of an instruction stream in a previously defined processor context, without enabling execution of the interrupt handler procedure.

2. The power sequence controller of claim 1, further including

sleep wakeup logic for evaluating, when the processor is in a sleep state, the processor'"'"'s sleep state so as to determine whether transitioning the processor from the current sleep state to the working state requires execution of a processor wakeup procedure to return the processor to the working state, and for generating a processor interrupt signal when the determination indicates that execution of the processor wakeup procedure is required.

3. The power sequence controller of claim 2, including a configuration register for storing a sleep state indicia for the processor, the processor'"'"'s sleep state indicia representing a sleep state specified by the processor before transitioning to the processor specified sleep state;

wherein the processor specified sleep state is one of a predefined plurality of sleep states, each distinct sleep state having associated therewith a distinct power usage state of the processor and a corresponding distinct wakeup protocol;

wherein the sleep wakeup logic retrieves the processor'"'"'s sleep state indicia from the configuration register when determining whether execution of the processor wakeup procedure is required.

4. The power sequence controller of claim 3, including a sleep state mask for storing a mask value indicating which of the predefined plurality of sleep states require execution of the processor wakeup procedure to return the processor to the working state;

wherein the sleep wakeup logic compares the sleep state indicia retrieved from the configuration register with the sleep state mask to determine whether execution of the processor wakeup procedure is required.

5. The power sequence controller of claim 1, further including

sleep wakeup logic for evaluating, when the processor is in a sleep state, the processor'"'"'s sleep state so as to determine whether transitioning the processor from the current sleep state to the working state requires execution of a processor wakeup procedure to return the processor to the working state, and for storing a non-zero value associated with the wakeup event signal in the interrupt source register when the determination indicates that execution of the processor wakeup procedure is required;

wherein,

the processor'"'"'s sleep state is one of a predefined plurality of sleep states, each distinct sleep state having associated therewith a distinct power usage state of the processor and a corresponding distinct wakeup protocol;

the predefined plurality of sleep states including at least one sleep state from which execution of an instruction stream in a previously defined context can be resumed without execution of the processor wakeup procedure and without execution of the interrupt handler procedure.

6. The power sequence controller of claim 1, further including:

processor reset logic for evaluating, when the processor is in a sleep state, the processor'"'"'s sleep state so as to determine whether the processor must be reset in order to return the processor to the working state, and for generating a processor reset signal when (A) the intercepted wakeup event signal requires transitioning the processor to the working state, as determined by the wakeup logic, and (B) the determination by the processor reset logic indicates that a processor reset is required;

wherein

the processor'"'"'s sleep state is one of a predefined plurality of sleep states, each distinct sleep state having associated therewith a distinct power usage state of the processor and a corresponding distinct wakeup protocol;

the predefined plurality of sleep states including at least one sleep state from which return to the working state requires said processor reset.

7. The power sequence controller of claim 6, including a configuration register for storing a sleep state indicia for the processor, the processor'"'"'s sleep state indicia representing a sleep state specified by the processor before transitioning to the processor specified sleep state;

wherein the processor specified sleep state is one of a predefined plurality of sleep states, each distinct sleep state having associated therewith a distinct power usage state of the processor and a corresponding distinct wakeup protocol;

wherein the processor reset logic retrieves the sleep state indicia from the configuration register when determining whether the processor must be reset.

8. The power sequence controller of claim 7, including a sleep state reset mask for storing a mask value indicating which of the predefined plurality of sleep states require the processor to be reset in order to return the processor to the working state;

wherein the processor reset logic compares the sleep state indicia retrieved from the configuration register with the sleep state reset mask to determine whether a processor reset is required.

9. A power management method for use in a device having a processor for executing instructions in an instruction stream, comprising the steps of:

storing a first wakeup mask indicating which of a predefined set of wakeup event signals are to be ignored and which require transitioning the processor from a sleep state to a working state;

storing a second wakeup indicating which of the predefined set of wakeup event signals require software processing;

comparing a wakeup event signal intercepted by a power sequence controller with the first wakeup mask and generating a processor wakeup signal when the comparison indicates that the intercepted wakeup event signal requires transitioning the processor to the working state; and

determining whether the intercepted wakeup event signal requires software processing, and storing a non-zero value associated with the wakeup event signal in an interrupt source register when the determination indicates that software processing is required;

wherein

the determining step includes comparing the intercepted wakeup event signal with the second wakeup mask to determine whether the intercepted wakeup event signal requires software processing;

the non-zero value in the interrupt source register causes the processor to execute an interrupt handler procedure and process the intercepted wakeup event; and

when a processor wakeup signal is generated in response to the intercepted wakeup event signal and the determining step determines that the intercepted wakeup event does not require software processing, the processor transitions to a working state so as to resume execution of an instruction stream in a previously defined processor context without executing the interrupt handler procedure.

10. The power management method of claim 9, further including

evaluating, when the processor is in a sleep state, the processor'"'"'s sleep state so as to determine whether transitioning the processor from the current sleep state to the working state requires execution of a processor wakeup procedure to return the processor to the working state, and generating a processor interrupt signal when the determination indicates that execution of the processor wakeup procedure is required.

11. The power management method of claim 10, including storing a sleep state indicia for the processor, the processor'"'"'s sleep state indicia representing a sleep state specified by the processor before transitioning to the processor specified sleep state;

wherein the processor specified sleep state is one of a predefined plurality of sleep states, each distinct sleep state having associated therewith a distinct power usage state of the processor and a corresponding distinct wakeup protocol;

wherein the sleep state evaluating step includes retrieving the stored sleep state indicia when determining whether execution of the processor wakeup procedure is required.

12. The power management method of claim 11, including storing a sleep state mask value indicating which of the predefined plurality of sleep states require execution of the processor wakeup procedure to return the processor to the working state;

wherein the sleep state evaluating step compares the retrieved sleep state indicia with the sleep state mask to determine whether execution of the processor wakeup procedure is required.

13. The power management method of claim 9, further including:

evaluating, when the processor is in a sleep state, the processor'"'"'s sleep state so as to determine whether transitioning the processor from the current sleep state to the working state requires execution of a processor wakeup procedure to return the processor to the working state, and storing a non-zero value associated with the wakeup event signal in the interrupt source register when the determination indicates that execution of the processor wakeup procedure is required;

wherein

the processor'"'"'s sleep state is one of a predefined plurality of sleep states, each distinct sleep state having associated therewith a distinct power usage state of the processor and a corresponding distinct wakeup protocol;

the predefined plurality of sleep states including at least one sleep state from which execution of an instruction stream in a previously defined context can be resumed without execution of the processor wakeup procedure and without execution of the interrupt handler procedure.

14. The power management method of claim 9, further including:

evaluating, when the processor is in a sleep state, the processor'"'"'s sleep state so as to determine whether the processor must be reset in order to return the processor to the working state, and generating a processor reset signal when (A) the intercepted wakeup event signal requires transitioning the processor to the working state, and (B) the determination by the sleep state evaluating step indicates that a processor reset is required;

wherein

the processor'"'"'s sleep state is one of a predefined plurality of sleep states, each distinct sleep state having associated therewith a distinct power usage state of the processor and a corresponding distinct wakeup protocol;

the predefined plurality of sleep states including at least one sleep state from which return to the working state requires said processor reset.

15. The power management method of claim 14, including storing in a register a sleep state indicia for the processor, the processor'"'"'s sleep state indicia representing a sleep state specified by the processor before transitioning to the processor specified sleep state;

wherein the sleep state evaluating step includes retrieving the stored sleep state indicia when determining whether the processor must be reset.

16. The power management method of claim 15, including storing a sleep state reset mask value indicating which of the predefined plurality of sleep states require the processor to be reset in order to return the processor to the working state;

wherein the sleep state evaluating step compares the retrieved sleep state indicia with the sleep state reset mask to determine whether said processor reset is required.