Integrated circuit

• US 5,878,331 A
• Filed: 07/30/1996
• Issued: 03/02/1999
• Est. Priority Date: 01/22/1996
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamamoto, Kazuya, Maemura, Kosei
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): RAO, ANAND SHASHIKANT
• Application Number:
  US08/689,085
• Time in Patent Office: 945 Days
• Field of Search: 455/78, 455/79, 455/80, 455/81, 455/83, 455/269, 455/281, 455/283, 455/106, 455/249.1, 455/252.1, 455/116, 455/82, 455/126, 455/127, 455/527, 333/17.1, 333/18, 333/104, 333/103, 333/262, 333/81, 330/277, 330/296, 330/136, 330/130
• US Class Current: 455/83
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

An integrated circuit includes a single pole double throw switch including a transmitting and receiving port, a transmitting port, and a receiving port. A transmission switch is coupled between the transmitting port and the transmitting and receiving port. A reception switch is coupled between the receiving port and the transmitting and receiving port. The reception switch includes a field effect transistor having a gate, a drain and a source. A voltage generating circuit receives first and second power supply voltages. The first power supply voltage is greater than the second power supply voltage. The voltage generating circuit generates a third voltage lower than the second power supply voltage and applies the third voltage to the gate of the field effect transistor of the reception switch during transmission. As a result, the magnitude of the voltage difference between the gate and the source or the gate and the drain of the second field effect transistor is greater than the magnitude of the difference between the first and second power supply voltages. Accordingly, because of the increased electrical separation between the terminals of the field effect transistor, leakage current flowing to the receiving port during transmission is reduced.

Claims

1. An integrated circuit including:

an SPDT (Single Pole Double Throw) switch comprising;

a transmitting and receiving port, a transmitting port, and a receiving port,

a transmission switch coupled between the transmitting port and the transmitting and receiving port, the transmission switch including a first field effect transistor having a gate and conducting current between the transmitting port and the transmitting and receiving port in response to a first control signal having a voltage substantially equal to a first power supply voltage applied to the gate of the first field effect transistor, and

a reception switch coupled between the receiving port and the transmitting and receiving port, the reception switch including a second field effect transistor having a gate, a drain, and a source and conducting current between the receiving port and the transmitting and receiving port in response to a second control signal having a voltage substantially equal to the first power supply voltage applied to the gate of the second field effect transistor; and

voltage generating means, receiving the first power supply voltage and receiving a second power supply voltage lower than the first power supply voltage, for generating a third voltage lower than the second power supply voltage, and applying the third voltage to the gate of the second field effect transistor when the first power supply voltage is applied to the gate of the first field effect transistor.

7. The integrated circuit according to claim 1 wherein the voltage generating means comprises:

an oscillator;

a drive circuit coupled to the oscillator for generating a drive signal and an inverted drive signal;

a charge pump circuit, coupled to the drive circuit, for generating the third voltage in response to the inverted drive signal.

8. The integrated circuit of claim 1 wherein, during transmission, a voltage difference between the gate of the second field effect transistor and the source of the second field effect transistor is greater in magnitude than a voltage difference

2. An integrated circuit comprising:

an SPDT (Single Pole Double Throw) switch comprising;

a transmitting and receiving port, a transmitting port, and a receiving port,

a transmission switch coupled between the transmitting port and the transmitting and receiving port, the transmission switch including a first field effect transistor having a gate and conducting current between the transmitting port and the transmitting and receiving port in response to a first control signal having a voltage substantially equal to a positive power supply voltage applied to the gate of the first field effect transistor, and

a reception switch coupled between the receiving port and the transmitting and receiving port, the reception switch including a second field effect transistor having a gate, and conducting current between the receiving port and the transmitting and receiving port in response to second control signal having a voltage substantially equal to the positive power supply voltage applied to the gate of the second field effect transistor;

means for applying a voltage lower than ground voltage to the gate of the second field effect transistor when the positive power supply voltage is applied to the gate of the first field effect transistor;

a reception attenuator including a third field effect transistor having a gate and connected to the receiving port of the SPDT switch, the reception attenuator being in a non-attenuating state when a third control signal having a voltage substantially equal to the positive power supply voltage is applied to the gate of the third field effect transistor and in an attenuating state when a voltage lower than the positive power supply voltage is applied to the gate of the third field effect transistor; and

means for applying the voltage lower than the ground voltage to the gate of the third field effect transistor to produce the attenuating state of the reception attenuator when the positive power supply voltage is applied to the gate of the first field effect transistor.

3. An integrated circuit including:

an SPDT (Single Pole Double Throw) switch comprising;

a transmitting and receiving port, a transmitting port, and a receiving port,

a transmission switch coupled between the transmitting port and the transmitting and receiving port, the transmission switch including a first field effect transistor having a gate and conducting current between the transmitting port and the transmitting and receiving port in response to a first control signal having a voltage substantially equal to a positive power supply voltage applied to the gate of the first field effect transistor, and

a reception switch coupled between the receiving port and the transmitting and receiving port, the reception switch including a second field effect transistor having a gate, a source, and a drain, and conducting current between the receiving port and the transmitting and receiving port in response to a second control signal having a voltage substantially equal to the positive power supply voltage applied to the gate of the second field effect transistor; and

means for applying ground voltage to the gate of the second field effect transistor and applying a voltage higher than the positive power supply voltage to the source and the drain of the second field effect transistor when the first field effect transistor is conducting.

5. The integrated circuit of claim 3 wherein the means for applying includes a voltage doubling circuit for producing the voltage higher than the positive power supply voltage.

4. An integrated circuit including:

an SPDT (Single Pole Double Throw) switch comprising;

a transmitting and receiving port, a transmitting port, and a receiving port,

a transmission switch coupled between the transmitting port and the transmitting and receiving port, the transmission switch including a first field effect transistor having a gate and conducting current between the transmitting port and the transmitting and receiving port in response to a first control signal having a voltage substantially equal to a positive power supply voltage applied to the gate of the first field effect transistor, and

a reception switch coupled between the receiving port and the transmitting and receiving port, the reception switch including a second field effect transistor having a gate, a source, and a drain, and conducting current between the receiving port and the transmitting and receiving port in response to a second control signal having a voltage substantially equal to the positive power supply voltage applied to the gate of the second field effect transistor; and

means for applying a voltage lower than ground voltage to the gate of the second field effect transistor and applying a voltage higher than the positive power supply voltage to the source and the drain of the second field effect transistor when the first field effect transistor is conducting.

6. The integrated circuit of claim 4 wherein the means for applying includes a voltage doubling circuit for producing the voltage higher than the positive power supply voltage.