Method for fabricating chip size packages using lamination process

• US 5,879,964 A
• Filed: 06/26/1998
• Issued: 03/09/1999
• Est. Priority Date: 07/07/1997
• Status: Expired due to Fees

• Current Assignee: Korea Advanced Institute of Science and Technology
• Original Assignee: Korea Advanced Institute of Science and Technology
• Inventors: Jang, Se Young, Paik, Kyung Wook
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/105,055
• Time in Patent Office: 256 Days
• Field of Search: 438/113, 438/107, 438/114, 438/460, 438/464, 438/465
• US Class Current: 438/113
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/351 Thermal stress

Abstract

A method for fabricating chip size packages which uses a lamination process, thereby not only achieving an improvement in the reliability of final electronic products, a reduction in the manufacturing costs, and a mass production resulting in a high marketability, but also being applicable to the fabrication of packages for both memory and non-memory chips and enabling the final electronic products to have high electronic performance while making the package size of the final electronic products not greater than 1.2 times the semiconductor chip size. The method includes the steps of cutting a wafer into a plurality of wafer strips each having several dies, arranging the wafer strips on an adhesive-coated polymer film supported by an annular frame in such a manner that they are aligned with each other while being uniformly spaced from one another, bonding the aligned wafer strips to the polymer film in accordance with a lamination process, forming a polymer dam made of an epoxy-based polymer on the polymer film around a wafer region, forming an encapsulant encapsulating the wafer strips, forming a double laminated polymer film to encapsulate the chips as an alternative encapsulation method, forming via holes at positions respectively corresponding to pads of chips through the polymer film, forming an array of I/O pads for the chips, fusing solder balls to the I/O pads, and cutting several ten dies integrally formed in one lot into separate packages.

Claims

1. A method for fabricating chip size packages, comprising the steps of:

cutting a wafer, on which desired circuit patterns have been formed, into a plurality of wafer strips each having several dies, using a diamond saw;

arranging the wafer strips on a stress reducing thermoplastic adhesive-coated polymer film supported by an annular frame in such a manner that they are aligned with each other while being uniformly spaced from one another by about 5 mm and in such a manner that the upper surface of each wafer strip faces the surface of the polymer film opposite to the annular frame;

bonding the aligned wafer strips to the polymer film in accordance with a lamination process;

forming a polymer dam made of an epoxy-based polymer on the surface of the polymer film, to which the wafer strips are bonded, around a wafer region where the wafer strips are disposed, filling an epoxy-based polymer in the wafer region defined by the polymer dam, thereby forming an encapsulant encapsulating the wafer strips, and curing the encapsulant;

forming a double laminated polymer film to encapsulate the chips as an alternative encapsulation method;

forming via holes at positions respectively corresponding to pads of chips through the polymer film, forming a solderable Ti/Ni/Cu metal thin film over the polymer film, forming a photoresist film over the solderable metal thin film, patterning the photoresist film, and patterning the metal thin film while using the patterned photoresist film as a mask, thereby forming an array of I/O pads for the chips;

coating a flux on the I/O pads, arranging solder balls on the I/O pads, respectively, fusing the solder balls to the associated I/O pads using a solder reflow oven, and removing the flux using an organic solvent; and

polishing the backside of the resulting epoxy encapsulated structure, and cutting several ten dies integrally formed in one lot into separate packages.