Semiconductor device and method for forming the same

• US 5,879,969 A
• Filed: 04/30/1997
• Issued: 03/09/1999
• Est. Priority Date: 03/06/1991
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei, Zhang, Hongyong
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Hawranek, Scott J.
• Application Number:
  US08/841,638
• Time in Patent Office: 678 Days
• Field of Search: 437/21, 437/40, 437/41, 437/236, 437/237, 437/71, 437/170, 437/195, 437/944, 148/DIG. 103, 148/DIG. 100, 148/DIG. 105, 148/DIG. 106, 205/123, 205/124, 205/157, 438/151, 438/163, 438/303, 438/595, 438/635, 438/768
• US Class Current: 438/151
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate electrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion. Further, an aluminum oxide or silicon nitride is formed as an etching stopper between the gate electrode and the gate insulating film or between the substrate and the layer on the substrate, so that the over-etching can be prevented and the flatness of the element can be improved. In addition, a contact is formed in no consideration of the concept "contact hole".

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming an electrode pattern on a substrate, said electrode pattern comprising an anodizable material;

forming a wiring on said substrate, said wiring being electrically connected to said electrode pattern and comprising a different material from said anodizable material;

performing an anodic oxidation to oxidize an exposed surface of said electrode pattern by feeding an electric field thereto through said wiring; and

selectively removing said wiring after performing said anodic oxidation to expose an unoxidized surface of said electrode pattern.

2. The method of claim 1 wherein said wiring is not anodized by said anodic oxidation.

3. The method of claim 2 wherein said wiring comprises a material selected from the group consisting of gold, titanium oxide, and indium oxide.

4. The method of claim 1 wherein said wiring is anodized by said anodic oxidation.

5. The method of claim 4 wherein said wiring comprises a metal selected from the group consisting of chromium and titanium.

6. The semiconductor device of claim 1 wherein said electrode pattern comprises a gate wiring and a gate electrode.

7. A method of manufacturing a semiconductor device comprising the steps of:

forming a first electrode pattern on a substrate, said first electrode pattern comprising an anodizable material;

forming a wiring on said substrate, said wiring being electrically connected to said electrode pattern and comprising a different material from said anodizable material;

performing an anodic oxidation to oxidize an exposed surface of said electrode pattern by feeding an electric field thereto through said wiring wherein a portion of said electrode pattern that is covered by said wiring is not oxidized;

selectively removing said wiring after performing said anodic oxidation to expose said portion of the electrode pattern; and

forming a second electrode in electrical contact with said portion of the electrode pattern.

8. A method of manufacturing a semiconductor device comprising the steps of:

forming an electrode pattern over a substrate, said electrode pattern comprising an oxidizable material;

forming a mask in electrical contact with said electrode pattern;

disposing said electrode pattern and said mask in an electrolyte for anodic oxidation; and

oxidizing an unmasked surface of said electrode to form an insulating layer thereon by applying an electric current to said electrode pattern through said mask in said electrolyte,

wherein said mask comprises a conductive material which has a higher resistivity against oxidation than said oxidizable material.

9. The method of claim 8 wherein said electrode pattern comprises aluminum.

10. The method of claim 8 wherein said conductive material is selected from the group consisting of chromium, gold, titanium, silicon, indium oxide, titanium oxide, indium-titanium oxide, and zinc oxide.

11. A method of manufacturing a semiconductor device comprising the steps of:

forming an electrode pattern comprising an anodizable metal over a substrate;

forming a conductive material in contact with said electrode pattern;

disposing said electrode pattern and said conductive material into an electrolyte for anodic oxidation;

conducting anodic oxidation in said electrolyte by applying an electric current to said electrode pattern through said conductive material,

wherein said conductive material is different from said anodizable metal.

12. A method of manufacturing a semiconductor device according to claim 11 wherein said conductive material is selected from the group consisting of chromium, titanium, silicon, indium oxide, titanium oxide, indium-titanium oxide, and zinc oxide.