Trench random access memory cell and method of formation

• US 5,879,971 A
• Filed: 09/28/1995
• Issued: 03/09/1999
• Est. Priority Date: 09/28/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Witek, Keith E.
• Primary Examiner(s): CHANG, JONI YUK YING
• Application Number:
  US08/535,865
• Time in Patent Office: 1,258 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/203, 257/903, 438/153, 438/238, 438/270, 438/268, 438/241, 438/242, 438/272
• US Class Current: 438/238
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment

Abstract

A method for forming a random access memory cell within four separate trench regions (106, 108, 110, and 112). One half of the memory cell has a first N-type transistor, which is a latch transistor (500), has a current electrode (101), a current electrode (126), and a gate electrode (114). A second N-type transistor, which is a word-line select transistor (504), has a first current electrode (101), a second current electrode (128), and a gate electrode (116). A P-channel pull up transistor (502) has a first current electrode (103), a second current electrode (124), and a gate electrode (114). The coupling of the electrodes (101 and 103) form a storage node of the one half of the memory cell which is contacted electrically by a conductive contact (140).

Claims

1. A method for forming a memory cell comprising the steps of:

providing a substrate, the substrate having a top surface segmented into a first top surface region, a second top surface region, a third top surface region, a fourth top surface region, a fifth top surface region, and a sixth top surface region, the substrate being made of a single crystalline semiconductive material;

forming a first transistor from the first top surface region, the first transistor having a substantially vertical current flow through a first channel region that is formed within the single crystalline semiconductive material of the substrate;

forming a second transistor from the second top surface region, the second transistor having a substantially vertical current flow through a second channel region that is formed within the single crystalline semiconductive material of the substrate;

forming a third transistor from the third top surface region, the third transistor having a substantially vertical current flow through a third channel region that is formed within the single crystalline semiconductive material of the substrate;

forming a fourth transistor from the fourth top surface region, the fourth transistor having a substantially vertical current flow through a fourth channel region that is formed within the single crystalline semiconductive material of the substrate;

forming a fifth transistor from the fifth top surface region, the fifth transistor having a substantially vertical current flow through a fifth channel region that is formed within the single crystalline semiconductive material of the substrate; and

forming a sixth transistor from the sixth top surface region, the sixth transistor having a substantially vertical current flow through a sixth channel region that is formed within the single crystalline semiconductive material of the substrate,

wherein the first through sixth vertical transistors are intercoupled to form the memory cell which retains a binary value.

2. The method of claim 1 wherein the step of providing the substrate comprises:

providing the first top surface region, the second top surface region, and the third top surface region such that the first top surface region is adjacent the second top surface region and the second top surface region is adjacent the third top surface region, wherein the first top surface region is separated from the third top surface region by the second top surface region.

3. The method of claim 1 wherein the step of providing the substrate comprises:

providing the fourth top surface region, the fifth top surface region, and the sixth top surface region such that the fourth top surface region is adjacent the fifth top surface region and the fifth top surface region is adjacent the sixth top surface region, wherein the fourth top surface region is separated from the sixth top surface region by the fifth top surface region.

4. The method of claim 1 wherein the steps of forming the first, second, and third transistors comprise:

forming the first transistor as a first N-channel transistor;

forming the second transistor as a first P-channel transistor; and

forming the third transistor as a second N-channel transistor wherein the first N-channel transistor and the first P-channel transistor are coupled to form an inverter and the second N-channel transistor is used as a word line select transistor for the memory cell.

5. The method of claim 4 wherein the steps of forming the fourth, fifth, and sixth transistors comprise:

forming the fourth transistor as a third N-channel transistor;

forming the fifth transistor as a second P-channel transistor; and

forming the sixth transistor as a fourth N-channel transistor wherein the third N-channel transistor and the second P-channel transistor are coupled to form an inverter and the fourth N-channel transistor is used as a word line select transistor for the memory cell.

6. The method of claim 1 wherein the step of providing the substrate comprises:

providing the first top surface region, the second top surface region, the third top surface region, the fourth top surface region, the fifth top surface region, and the sixth top surface region wherein none of the first top surface region, the second top surface region, the third top surface region, the fourth top surface region, the fifth top surface region, and the sixth top surface region overlie another of the first top surface region, the second top surface region, the third top surface region, the fourth top surface region, the fifth top surface region, and the sixth top surface region.

7. The method of claim 1 further comprising:

coupling the first, second, and third transistors to a first common storage node within the substrate; and

coupling the fourth, fifth, and sixth transistors to a second common storage node within the substrate wherein the first common storage node is physically separated from the second common storage node.

8. The method of claim 7 wherein the steps of coupling comprise:

forming one of either the first common storage node or the second common storage node as a P-type buried region coupled to an N-type buried layer.

9. The method of claim 7 further comprising:

forming a silicide region as part of either the first common storage node or the second common storage node.

10. The method of claim 7 further comprising:

forming a first contact to the first common storage node through the second top surface region; and

forming a second contact to the second common storage node through the fifth top surface region.

11. The method of claim 1 further comprising:

forming a first gate electrode as a first conductive sidewall spacer wherein both the first and second transistors are gated by the first gate electrode; and

forming a second gate electrode as a second conductive sidewall spacer wherein both the fourth and fifth transistors are gated by the second gate electrode.

12. The method of claim 11 further comprising:

forming a third gate electrode as a third conductive sidewall spacer wherein the third transistor is gated by the third gate electrode; and

forming a fourth gate electrode as a fourth conductive sidewall spacer wherein the sixth transistor is gated by the fourth gate electrode.

13. The method of claim 12 further comprising:

etching the third conductive sidewall spacer such that the third gate electrode has a first portion with a first height and a second portion with a second height, the first height being different from the second height; and

etching the fourth conductive sidewall spacer such that the fourth gate electrode has a first portion with a first height and a second portion with a second height, the first height being different from the second height.

14. The method of claim 1 further comprising:

forming a first trench region wherein the first and second transistors are formed adjacent a sidewall of the first trench region; and

forming a second trench region wherein the fourth and fifth transistors are formed adjacent a sidewall of the second trench region, the first trench region and the second trench region being physically separated from on another.

15. The method of claim 14 further comprising:

forming a third trench region wherein the third transistor is formed adjacent a sidewall of the third trench region; and

forming a fourth trench region wherein the sixth transistor is formed adjacent a sidewall of the fourth trench region, the third trench region and the fourth trench region being physically separated from on another.

16. A method for forming a random access memory comprising the steps of:

providing a substrate made of single crystalline material, the substrate having a top surface;

forming two N-type select transistors within the single crystalline material of the substrate wherein each of the two N-type select transistors have a vertical current flow through a vertically-oriented channel region, each of the two N-type select transistors being formed substantially below the top surface of the substrate and being electrically coupled to allow for reading of both a bit value and a complementary bit value from the random access memory;

forming two N-type latch transistors within the single crystalline material of the substrate wherein each of the two N-type latch transistors have a vertical current flow through a vertically-oriented channel region, each of the two N-type latch transistors being formed substantially below the top surface of the substrate and being electrically coupled as part of a circular-coupled pair of inverters wherein the circular-coupled pair of inverters is used to store the bit value and the complementary bit value; and

forming two P-type pull-up transistors within the single crystalline material of the substrate wherein each of the two P-type pull-up transistors have a vertical current flow through a vertically-oriented channel region, each of the two P-type pull-up transistors being formed substantially below the top surface of the substrate and being electrically coupled as part of the circular-coupled pair of inverters wherein the circular-coupled pair of inverters is used to store the bit value and the complementary bit value, one of the two P-type pull-up transistors and one of the N-type latch transistors being formed together in a trench, where the trench has a contiguous sidewall periphery made of the single crystalline material from the substrate and where a first portion of this contiguous sidewall periphery is used to form the one of the two P-type pull-up transistors and a second portion of the contiguous sidewall periphery is used to form the one of the two N-type latch transistors.

17. The method of claim 16 wherein the steps of forming two P-type pull-up transistors and forming two N-type latch transistors comprise:

forming one of the two P-type pull-up transistors and one of the two N-type latch transistors adjacent a first trench region wherein a first half of the first trench region functions as a channel region for the one of the two P-type pull-up transistors and a second half of the first trench region functions as a channel region for the one of the two P-type pull-up transistors; and

forming another of the two P-type pull-up transistors and another of the two N-type latch transistors adjacent a second trench region wherein a first half of the second trench region functions as a channel region for the another of the two P-type pull-up transistors and a second half of the second trench region functions as a channel region for the another of the two P-type pull-up transistors.

18. The method of claim 17 wherein the step of forming two N-type select transistors comprises:

forming one of the two N-type select transistors adjacent a third trench region; and

forming another of the two N-type select transistors adjacent a fourth trench region.

19. The method of claim 18 wherein the first through fourth trench regions are physically separated from one another.

20. The method of claim 17 wherein the steps of forming two N-type select transistors, forming two N-type latch transistors, and forming two P-type pull-up transistors comprise:

forming the one of the two N-type select transistors, the one of the forming two P-type pull-up transistors, and the one of the two N-type latch transistors all coupled to a first common buried layer formed within the substrate, the first common buried layer retaining a binary value when electrically operating; and

forming the another of the two N-type select transistors, the another of the forming two P-type pull-up transistors, and the another of the two N-type latch transistors all coupled to a second common buried layer formed within the substrate, the second common buried layer retaining a complimentary binary value that is a logical complement of the binary value when electrically operating.

21. The method of claim 20 wherein comprising the step of:

forming an electrical contact to the first common buried layer by etching an opening through the substrate to expose the first common buried layer, the opening being in close proximity to the first trench region.

22. The method of claim 16 wherein the steps of forming two N-type select transistors, forming two N-type latch transistors, and forming two P-type pull-up transistors comprise:

forming one of the two N-type select transistors, one of the forming two P-type pull-up transistors, and one of the two N-type latch transistors all coupled to a first common buried layer formed within the substrate, the first common buried layer retaining a binary value when electrically operating; and

forming another of the two N-type select transistors, another of the forming two P-type pull-up transistors., and another of the two N-type latch transistors all coupled to a second common buried layer formed within the substrate, the second common buried layer retaining a complimentary binary value that is a logical complement of the binary value when electrically operating.

23. The method of claim 16 wherein the step of forming two N-type select transistors comprises:

forming one of the two N-type select transistors having a channel region laterally adjacent a first trench region; and

forming another of the two N-type select transistors having a channel region laterally adjacent a second trench region.

24. A method for forming a memory cell comprising the steps of:

providing a substrate;

forming a first trench region within the substrate, the first trench region defining a first semiconductor substrate sidewall portion and a second semiconductor sidewall portion wherein the first semiconductor sidewall portion is opposite the second semiconductor sidewall portion, the first trench region being used to form a first N-channel transistor within the first semiconductor substrate sidewall portion and a first P-channel transistor of the memory cell within the second semiconductor substrate sidewall portion;

forming a second trench region within the substrate, the second trench region defining a third semiconductor substrate sidewall portion and a fourth semiconductor sidewall portion wherein the third semiconductor sidewall portion is opposite the fourth semiconductor sidewall portion, the second trench region being used to form a second N-channel transistor within the third semiconductor substrate sidewall portion and a second P-channel transistor of the memory cell within the fourth semiconductor substrate sidewall portion;

forming a third trench region within the substrate, the third trench region being used to form a third N-channel transistor of the memory cell;

forming a fourth trench region within the substrate, the fourth trench region being used to form a fourth N-channel transistor of the memory cell; and

electrically intercoupling the first N-channel transistor, the second N-channel transistor, the third N-channel transistor, the fourth N-channel transistor, the first P-channel transistor, and the second P-channel transistor to form the memory cell which stores a binary value of information.

25. The method of claim 24 wherein the step of electrically intercoupling comprises:

forming a first doped buried region below a top surface of the substrate, the first doped buried region lying between the first trench region and the third trench region wherein the first N-channel transistor, the first P-channel transistor, and the third N-channel transistor all couple to the first doped buried region.

26. The method of claim 25 wherein the step of electrically intercoupling comprises:

forming an opening through the substrate to expose the first doped buried region; and

forming an electrical contact within the first doped buried region to contact the first doped buried region as a storage node which stores a binary value.

27. The method of claim 26 wherein the step of electrically intercoupling comprises:

forming a dielectric sidewall spacer within the opening before forming the electrical contact.

28. The method of claim 26 wherein the step of electrically intercoupling comprises:

ion implanting dopant atoms into the first doped buried region through the opening.

29. The method of claim 26 wherein the step of electrically intercoupling comprises:

etching the opening through a conductive member which supplies the first P-channel transistor with a power supply voltage.

30. The method of claim 24 wherein the first through fourth N-channel transistors and the first through second P-channel transistors are formed each having a channel region through which a current flow passes in a direction substantially perpendicular to a top surface of the substrate.

31. The method of claim 24 wherein the second N-channel transistor is a first select transistor for the memory cell which is gated by a first word line and the fourth N-channel transistor is a second select transistor for the memory cell which is gated by a second word line, the first and second word lines being electrically coupled to one another.

32. A method for forming a portion of a memory cell comprising the steps of:

providing a substrate;

forming a first trench region within the substrate, the first trench region having a sidewall, a top portion, a bottom portion, a first half of the first trench region, and a second half of the first trench region;

forming a first N-type current electrode at the bottom portion of the first trench region;

forming a second N-type current electrode at the top portion of the first trench region and adjacent the first half of the first trench region wherein a first channel region lies between the first N-type current electrode and the second N-type current electrode;

forming a first annular sidewall spacer within the first trench region and laterally adjacent the sidewall of the first trench region, the first annular sidewall spacer controlling a current flow through the first channel region;

forming a first P-type current electrode adjacent and in electrical contact with the first N-type current electrode wherein the first P-type current electrode is located at the bottom portion of the first trench region;

forming a second P-type current electrode at the top portion of the first trench region and adjacent the second half of the first trench region, the second P-type current electrode being isolated from the second N-type current electrode by the first trench region, wherein a second channel region lies between the first P-type current electrode and the second P-type current electrode where the second channel region has a current flow controlled by the first annular sidewall spacer;

forming a second trench region within the substrate, the second trench region having a sidewall, a top portion, a bottom portion, a first half of the second trench region, and a second half of the second trench region, the second trench region being formed so that the first N-type current electrode is adjacent the bottom portion of the second trench region;

forming a third N-type current electrode at the top portion of the second trench region and within the first half of the second trench region, a third channel region being defined adjacent the sidewall of the second trench region and between the first N-type current electrode and the third N-type current electrode; and

forming a second annular sidewall spacer adjacent the sidewall of the second trench region wherein the second sidewall spacer controls a current flow through the third channel region.

33. The method of claim 32 wherein step of forming the first N-type current electrode at the bottom portion of the first trench region comprises:

forming the first N-type current electrode by ion implanting N-type dopants into the substrate; and

growing epitaxial material over the N-type dopants to form the first N-type current electrode as N-type buried region.

34. The method of claim 33 wherein step of forming the first N-type current electrode at the bottom portion of the first trench region comprises:

forming the first N-type current electrode before the step of forming the first trench region.

35. The method of claim 33 wherein step of forming a first P-type current electrode adjacent comprises:

forming the first P-type current electrode by ion implanting P-type dopants into the substrate above the first N-type current electrode; and

growing epitaxial material over the P-type dopants to form the first P-type current electrode as a P-type buried region which is in contact with the first N-type buried region.

36. The method of claim 32 wherein step of forming a first P-type current electrode adjacent comprises:

forming the first P-type current electrode by ion implanting P-type dopants into the substrate laterally adjacent the first N-type current electrode; and

growing epitaxial material over the P-type dopants and the first N-type current electrode to form the first P-type current electrode as a P-type buried region and form the first N-type current electrode as an N-type buried layer.

37. The method of claim 32 further comprising the step of:

forming a silicided layer between the first P-type current electrode and the first N-type current electrode to reduce a diode voltage drop between the first P-type current electrode and the first N-type current electrode.

38. The method of claim 32 further comprising the step of:

filling the first trench region with a dielectric plug material which is adjacent the first annular sidewall spacer.

39. The method of claim 32 further comprising the step of:

filling the second trench region with a dielectric plug material which is adjacent the second annular sidewall spacer.

40. The method of claim 32 further comprising the step of:

reducing a height of a portion of the second annular sidewall spacer such that the second annular sidewall spacer has a first portion with a first height and a second portion with a second height, the first height being unequal to the second height.

41. The method of claim 32 further comprising the step of:

forming a contact to the first N-type current electrode by etching an opening between the first trench region and the second trench region which exposes a portion of the first N-type current electrode.

42. A method for forming an SRAM memory cell circuit, the method comprising:

providing a substrate having a top surface;

forming an N-type select transistor having a vertical channel region which is designed to generate vertical transistor current flow through a first single-crystalline silicon-containing region in a direction substantially perpendicular to the top surface of the substrate;

forming an N-type latch transistor having a vertical channel region which is designed to generate vertical transistor current flow through a second single-crystalline silicon-containing region in a direction substantially perpendicular to the top surface of the substrate; and

forming a P-type pull-up device having a vertical channel region which is designed to generate vertical device current flow through a third single-crystalline silicon-containing region in a direction substantially perpendicular to the top surface of the substrate, wherein the P-type pull-up device, the N-type latch transistor, and the N-type select transistor are coupled together at a common circuit node, the P channel transistor located entirely between the N-type latch transistor and the N-type select transistor.

43. The method of claim 42 wherein the first single-crystalline silicon-containing region is formed within an annular substrate sidewall of a first opening formed into the substrate and the second and third single-crystalline silicon-containing regions are formed on opposite halves of an annular substrate sidewall of a second opening formed into the substrate.

44. The method of claim 42 wherein the first single-crystalline silicon-containing region is adjacent the third single-crystalline silicon-containing region and the second single-crystalline silicon-containing region is adjacent the third single-crystalline silicon-containing region with the third single-crystalline silicon-containing region separating the first and second single-crystalline silicon-containing regions.

45. The method of claim 42 wherein the first single-crystalline silicon-containing region is formed in a first half of a circumference of an opening formed in the substrate and the second single-crystalline silicon-containing region is formed in a second half of the circumference of the opening formed in the substrate.

46. The method of claim 45 wherein the third single-crystalline silicon-containing region lies within the opening formed within the substrate.

47. A method for forming a memory cell circuit, the method comprising the steps of:

providing a substrate having a plurality of trenches in the substrate to define a plurality of sidewalls of the substrate;

forming a first N-type transistor from a first sidewall of the substrate;

forming a second N-type transistor from a second sidewall of the substrate;

forming a first P-type transistor from a third sidewall of the substrate; and

forming a doped PN junction node within the substrate to which at least two of the first N-type transistor, second N-type transistor, and the P-type transistor are coupled.

48. The method of claim 47 wherein the PN junction contains a metallic region between a P-type region and an N-type region of the PN junction to reduce a voltage drop across the PN junction.

49. A method for forming a memory cell, the method comprising the steps of:

forming six transistors within a single-crystalline contiguous substrate to form the memory cell wherein each of the six transistors is a vertical MOS transistor having a channel region formed within the an outer periphery of a trench region formed within the single-crystalline contiguous substrate and wherein both the source and drain for each transistor in the six transistors are also formed within the single-crystalline contiguous substrate.

50. The method of claim 49 wherein all the channel regions for all of the six transistors lies adjacent a gate oxide formed adjacent a sidewall of a trench region formed within the substrate.