Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile

• US 5,879,975 A
• Filed: 09/05/1997
• Issued: 03/09/1999
• Est. Priority Date: 09/05/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ibok, Effiong, Ju, Dong-Hyuk, Bell, Scott A., Steckert, Daniel A., Ogle, Robert, Karlsson, Olov
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/924,322
• Time in Patent Office: 550 Days
• Field of Search: 438/585, 438/592, 438/659, 438/660, 438/162, 438/669, 438/705, 438/719, 438/720, 438/532
• US Class Current: 438/162
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/32137 of silicon-containing layers

Abstract

The etch profile of side surfaces of a gate electrode is improved by heat treating the gate electrode layer after nitrogen implantation and before etching to form the gate electrode. Nitrogen implantation at high dosages to prevent subsequent impurity penetration through the gate dielectric layer, e.g., B penetration, amorphizes the upper portion of the gate electrode layer resulting in concave side surfaces upon etching to form the gate electrode. Heat treatment performed after nitrogen implantation can restore sufficient crystallinity so that, after etching the gate electrode layer, the side surfaces of the resulting gate electrode are substantially parallel.

Claims

1. A method of manufacturing a semiconductor device, which method comprises:

forming a polycrystalline silicon layer on an upper surface of a semiconductor substrate with a dielectric layer therebetween;

implanting nitrogen atoms into the polycrystalline silicon layer at a dosage sufficient to amorphize an upper portion of the polycrystalline silicon layer;

heat treating said nitrogen implanted polycrystalline silicon layer under conditions sufficient to restore crystallinity to the amorphized upper portion of the polycrystalline silicon layer; and

etching the heat treated nitrogen implanted layer to form a gate electrode, wherein said heat treating improves the etch profile of the gate electrode.

2. The method according to claim 1, comprising implanting nitrogen at a dosage sufficient to amorphize the upper portion extending up to about 50% of the polycrystalline silicon gate electrode layer toward the upper surface of the semiconductor substrate.

3. The method according to claim 1, comprising:

etching the polycrystalline silicon layer to form a gate electrode having substantially parallel side surfaces.

4. The method according to claim 3, comprising etching the polycrystalline silicon layer to form a gate electrode having side surfaces substantially perpendicular to the upper surface of the semiconductor substrate.

5. The method according to claim 3, comprising heat treating the nitrogen implanted polycrystalline silicon layer at a temperature of about 600°

C. to about 1,000°

C.

6. The method according to claim 5, comprising heat treating the nitrogen implanted polycrystalline silicon layer at a temperature of about 850°

C. for about 30 seconds in an atmosphere comprising nitrogen and about 10 volume percent oxygen.

7. The method according to claim 5, comprising heat treating the nitrogen implanted polycrystalline silicon layer at a temperature of about 750°

C. for about 30 minutes in a nitrogen atmosphere.

8. The method according to claim 1, further comprising:

forming a mask on the nitrogen implanted polycrystalline silicon layer after heat treating; and

etching the heat treated masked polycrystalline silicon layer to form the gate electrode.

9. The method according to claim 1, wherein the semiconductor substrate comprises an N-type impurity.

10. The method according to claim 9, further comprising forming P-impurity type source/drain regions in the semiconductor substrate on opposite sides of the gate electrode to form a P-channel MOS.

11. The method according to claim 1, comprising:

implanting nitrogen under conditions sufficient to amorphize an upper portion of the polycrystalline silicon layer;

heat treating to restore sufficient crystallinity to the amorphized upper portion to enable formation of a gate electrode having substantially parallel side surfaces upon etching the polycrystalline silicon film; and

etching the polycrystalline silicon film to form a gate electrode having substantially parallel side surfaces.

12. The method according to claim 11, comprising etching the heat treated polycrystalline silicon film to form a gate electrode having side surfaces substantially perpendicular to the upper surface of the semiconductor substrate.

13. The method according to claim 1, wherein the dielectric layer has a thickness less than about 60 Å

.

14. The method according to claim 1, comprising heat treating the nitrogen implanted polycrystalline silicon layer before depositing any layer thereon.