Self-aligned method of fabricating terrace gate DMOS transistor

• US 5,879,994 A
• Filed: 04/15/1997
• Issued: 03/09/1999
• Est. Priority Date: 04/15/1997
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bencuya, Izak, Kwan, Sze-Hon, Sapp, Steven P.
• Primary Examiner(s): Booth, Richard A.
• Assistant Examiner(s): Hack, Jonathan
• Application Number:
  US08/842,661
• Time in Patent Office: 693 Days
• Field of Search: 438/975, 438/268, 438/585, 438/148, 438/DIG. 126
• US Class Current: 438/268
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 148/126 Power FETs
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed. Gate-drain capacitance caused by polysilicon gate overlap of the substrate is minimized as the overlap is minimized. Because input capacitance is reduced, switching speed is increased. This self-aligned feature also results in a smaller cell pitch dimension and higher packing density. Therefore, the specific ON resistance is reduced and current driving capacity is also greatly elevated.

Claims

1. A method of fabricating a terrace gate DMOS transistor comprising the steps of:

providing a semiconductor substrate having a substrate surface containing impurities of a first conductivity type;

forming a field oxide layer on the substrate surface;

forming a first photoresist mask on the field oxide layer, thereby defining first mask protected areas and first mask exposed areas, wherein the first mask protected areas include a terrace gate area and a device gate separation area, and wherein the first mask exposed areas include a device active area;

performing an etch of the field oxide layer through the first photoresist mask within the first mask exposed area to the substrate surface;

forming a thin layer of gate oxide on the substrate surface within the device active area;

depositing a polysilicon layer;

forming a second photoresist mask on the polysilicon layer, thereby defining second mask protected areas and second mask exposed areas, wherein the second mask protected areas fully overlie the terrace gate area such that the second mask protected area is larger than the terrace gate area and overlaps the terrace gate area by a non-zero overlap distance, and wherein the second mask exposed area includes the gate separation area; and

etching the polysilicon layer so as to fully remove it within the gate separation area, thereby exposing the field oxide layer.

2. A method as in claim 1, wherein the step of depositing a polysilicon layer includes depositing a polysilicon layer at least as thick as a device action area width, and wherein the method further comprises the step of, after the step of depositing the polysilicon layer, etching the polysilicon layer down to a polysilicon gate thickness.

3. A method as in claim 2, wherein the polysilicon gate thickness is approximately 5000 Angstroms.

4. A method as in claim 2, further comprising the step of performing an etch, thereby substantially reducing field oxide layer thickness within the gate separation area.

5. A method as in claim 4, further comprising the step of performing a thermal oxidation to form an implant oxide layer in the gate separation area.

6. A method as in claim 2, further comprising the steps of:

implanting impurities of a second conductivity type into the gate separation area; and

performing a drive-in diffusion heat cycle so as to form a channel region and a lightly-doped body region of a second conductivity type.

7. A method as in claim 2, further comprising the steps of:

forming a third photoresist mask exposing a heavy body implant region; and

implanting impurities of a second conductivity type through the third mask to form a lightly doped body region.

8. A method as in claim 7, further comprising the steps of:

forming a fourth photoresist mask exposing source implant regions; and

implanting impurities of a first conductivity type through the fourth photoresist mask to form source regions within the lightly doped body region.

9. A method as in claim 8, further comprising the step of depositing a dielectric interlayer.

10. A method as in claim 9, further comprising the steps of:

forming a fifth photoresist mask exposing source contact regions; and

etching the dielectric interlayer and oxide in the source contact regions back to the substrate surface.

11. A method as in claim 10, further comprising the step of depositing a source metal layer.

12. A method as in claim 6, wherein the first conductivity type is n type, and the second conductivity type is p type.

13. A method as in claim 12, wherein the step of providing a semiconductor substrate includes the steps of:

providing a heavily doped substrate of a first conductivity type; and

forming an epitaxial layer of the first conductivity type on the heavily doped substrate, such that the epitaxial layer has a lower doping concentration than the heavily doped substrate.

14. A method as in claim 13, wherein the forming of the epitaxial layer is performed by vapor-phase growth.

15. A method as in claim 2, wherein the step of performing an etch of the field oxide layer through the first photoresist mask includes an anisotropic etch.

16. A method as in claim 4, wherein the step of performing an etch includes performing an oxide-selective etch, such that field oxide layer thickness is decreased without affecting the polysilicon layer thickness.

17. A method as in claim 9, wherein the step of depositing a dielectric interlayer includes depositing phosphosilicate or borophosphosilicate glass.