Adaptively controlled, self-aligned, short channel device and method for manufacturing same

• US 5,879,998 A
• Filed: 07/09/1997
• Issued: 03/09/1999
• Est. Priority Date: 07/09/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Krivokapic, Zoran
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US08/890,388
• Time in Patent Office: 608 Days
• Field of Search: 438/259, 438/289, 438/291, 438/300, 438/589, 438/595, 438/174, 438/180, 438/182, 438/184, 438/694, 438/696
• US Class Current: 438/300
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location

Abstract

A short channel semiconductor device having source and drain regions in a substrate and a gate region on the top surface of the substrate between the source and drain regions is disclosed. In one embodiment, the method comprises: forming a device area in the silicon by forming a pattern stack, and forming pattern spacers adjacent to the pattern stack; forming a trench isolation about the pattern stack; removing the pattern spacers; depositing an epitaxial layer over the trench oxide and adjacent to the pattern stack; removing the pattern stack; and forming adaptively controlled spacers in the region to control said short channel length of the device.

The apparatus of the present invention comprises: a semiconductor substrate; a source region and a drain region formed in the substrate; a gate region, comprising a first and a second oxide regions, a first control spacer and a second control spacer positioned above the substrate and adjacent to the first and second oxide regions, respectively, and a polysilicon layer positioned between the spacers; and an epitaxial layer, adjacent to the source and drain region and surrounding said first and second spacers.

Claims

1. A method of manufacturing a short channel semiconductor device, comprising:

(A) forming a device area in the silicon by;

(1) forming a pattern stack;

(2) forming pattern spacers adjacent to the pattern stack;

(B) forming a trench isolation about the pattern stack;

(C) removing the pattern spacers;

(D) depositing an epitaxial layer over the trench isolation and adjacent to the pattern stack;

(E) removing the pattern stack to define a device region; and

(F) forming channel control spacers in the device region, each channel control spacer having a width selected to control a channel length in said short channel device.

2. The method of claim 1 wherein said control spacers are composed of a nitride.

3. The method of claim 2 wherein said control spacers have a width of between about 0.05 μ

m and 0.15 μ

m.

4. The method of claim 1 wherein said step A(1) comprises the sub-steps of:

sequentially depositing a first oxide layer, a first nitride layer, a second oxide layer and a second nitride layer on said substrate, each said layer having a layer length, a layer width and a layer height, said second nitride layer having a second nitride layer top surface;

masking the layer length of said first and second oxide layers and said first and second nitride layers; and

etching the first oxide layer, first nitride layer, second nitride layer and second oxide layer.

5. The method of claim 1 wherein said step (A)(2) comprises the sub-steps of:

(i) forming oxide spacers about the pattern stack; and

(ii) forming nitride spacers about the oxide spacers.

6. The method of claim 5 wherein:

said step (i) comprises;

forming a first oxide spacer layer along the pattern stack, said first oxide spacer layer having a first oxide spacer lateral surface,

selectively masking said first spacer oxide layer, and

etching said first oxide spacer layer; and

said step (ii) comprises;

forming a first nitride spacer layer along the pattern stack, said first nitride spacer layer having a first nitride spacer lateral surface, and

etching said first nitride spacer layer.

7. The method of claim 1 wherein said step (B) comprises:

forming an oxide trench into said substrate;

depositing a trench oxide into said oxide trench, said trench oxide having a trench oxide top surface; and

polishing the trench oxide top surface to said second nitride layer.

8. The method of claim 1, further including the step, between said steps (B) and (C), of:

removing a portion of the trench oxide layer to form a lowered trench oxide layer.

9. The method of claim 1 further including the step of:

(G) forming a source and drain region by depositing an impurity into the epitaxial layer and heating the substrate.

10. The method of claim 9 further including the step of:

(H) forming a local interconnect layer coupled to said source and drain regions.

11. The method of claim 1 wherein said control spacers have a width of between about 0.05 μ

m and 0.15 μ

m.

12. A method for making a semiconductor device, comprising:

(A) sequentially depositing a first oxide layer, a first nitride layer, a second oxide layer and a second nitride layer on said substrate, each said layer having a layer length, a layer width and a layer height, said second nitride layer having a second nitride layer top surface;

(B) etching the layer length of said first and second oxide layers and said first and second nitride layers to form pattern stack on the surface of the substrate;

(C) forming a first oxide spacer along the pattern stack;

(D) forming a first nitride spacer along the first oxide spacer;

(E) etching an oxide trench into said substrate;

(F) depositing a trench oxide into said oxide trench;

(G) etching said trench oxide, said second nitride layer and said first nitride spacer layer to remove said second nitride layer and said first nitride spacer layer and form a lowered trench oxide having a lowered trench oxide top surface;

(H) forming a selective epitaxial overgrowth layer on said lowered trench oxide top surface and on said substrate;

(I) removing said second oxide layer, said first nitride layer and said first oxide spacer layer to form a gate region, said gate region having gate region sidewalls adjacent to said selective epitaxial overgrowth layer and a gate region bottom overlying said first oxide layer;

(J) selectively depositing control spacers within said gate region; and

(K) implanting an impurity into the epitaxial layer and diffusing the impurity to form a source region and a drain region within said substrate.

13. The method of claim 12 further including the step, following step (J), of implanting an impurity to form a threshold voltage implant region.

14. The method of claim 12 further including the step, following step (J), of implanting an impurity to form a punch through stop implant region.

15. The method of claim 12 further including the steps, following step (J), of:

(J1) forming gate oxide layer;

(J2) depositing a polysilicon layer within said gate region, said polysilicon layer being adjacent to said adaptively controlled spacers; and

(J3) polishing said polysilicon layer to a level coincident with the control spacers.

16. The method of claim 12 wherein said step (C) comprises depositing a spacer oxide layer and selectively masking said spacer oxide layer, said first oxide spacer layer having a first oxide spacer lateral surface.

17. The method of claim 12 wherein said step (D) comprises depositing a spacer nitride layer and selectively masking said spacer nitride layer, said first nitride spacer layer having a first nitride spacer lateral surface.

18. The method of claim 12, further including the step, after step (J), of implanting an impurity into the epitaxial layer s within said substrate, said implants including a threshold voltage implant and a punch through stop implant.

19. The method of claim 12 further including the steps, following step J, of:

(J1) forming implants within said substrate, said implants including a threshold voltage implant and a punch through stop implant;

(J2) forming gate oxide layer;

(J3) depositing a polysilicon layer within said gate region, said polysilicon layer being adjacent to said adaptively controlled spacers;

(J4) polishing said polysilicon layer to said third oxide layer; and

(J5) forming source and drain regions overlapping said gate region by implanting a first conductivity type into said substrate.

20. The method of claim 12, further including the step of:

forming a local interconnect layer above said final selective epitaxial overgrowth layer.