Ultrathin electronics

• US 5,880,010 A
• Filed: 01/31/1997
• Issued: 03/09/1999
• Est. Priority Date: 07/12/1994
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Davidson, Howard L.
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US08/792,282
• Time in Patent Office: 767 Days
• Field of Search: 438/622, 438/455, 438/458, 438/459, 438/975, 438/977, 438/7, 438/74
• US Class Current: 438/455
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01031 Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10S 438/975 : Substrate or mask aligning feature
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated circuit comprises a plurality of active layers coupled together in close proximity. In order to produce the integrated circuit, at least two active layers are removed from their respective substrate after integrated circuit processing. Some of the methods that may be used include Silicon on Insulator ("SOI") and epitaxial etch stop ("EES") processes. After removal of the active layers, at least one via is implemented on a bottom surface of each active layer in order to establish a mechanical and electrical connection between the via and its associated metal interconnects. Thereafter, the active layers are coupled together by ultrasonic welding or through nitride lamination using Titanium Nitride for conductive regions and Silicon Nitride for insulative regions.

Claims

1. A method for coupling a first active layer of a first semiconductor device and a second active layer of a second semiconductor device in which both said first and second active layers function as complete integrated circuits, the method comprising the steps of:

removing said first active layer from said first semiconductor device and said second active layer from said second semiconductor device, at least the first active layer including a first layer of a transparent insulative material, a second layer of epitaxial partially deposited over said insulative material, and a metal interconnect partially placed over the first and second layer;

forming a first interconnect via on a bottom surface of said first active layer by a via lamination process;

forming a second interconnect via on a bottom surface of said second active layer; and

joining said first active layer and said second active layer by (i) visually aligning a first pad on said first active layer with a second pad on said second active layer by viewing through a portion of the insulative material not covered by one of the second layer and metal interconnect, and (ii) electrically coupling said first active layer with said second active layer.

2. The method according to claim 1, wherein after said step of forming said first interconnect via, said method further includes the step of:

electrically and mechanically coupling said first interconnect via on said bottom surface of said first active layer to a metal interconnect on a top surface of said first active layer.

3. The method according to claim 2, wherein after said step of forming said second interconnect via, said method further includes the step of:

electrically and mechanically coupling said second interconnect via on said bottom surface of said second active layer to a metal interconnect on a top surface of said second active layer.

4. The method according to claim 3, wherein said joining step includes the steps of:

aligning said first interconnect via of said first active layer and said second interconnect via of said second active layer so that said first pad associated with said first interconnect via of said first active layer is disposed generally opposite to said second pad associated with said second interconnect via of said second active layer; and

coupling said first pad to said second pad to establish an electrical connection from said metal interconnect on said top surface of said first active layer to said metal interconnect on said top surface of said second active layer.

5. The method according to claim 3, wherein said joining step includes the steps of:

aligning said first interconnect via of said first active layer and said metal interconnect of said second active layer so that said first pad associated with said first interconnect via of said first active layer is disposed generally opposite to a said second pad associated with said metal interconnect of said second active layer; and

coupling said first pad to said second pad to establish an electrical connection from said metal interconnect on said top surface of said first active layer to said second interconnect via on said bottom surface of said second active layer.

6. The method according to claim 3, wherein said joining step includes the steps of:

aligning said metal interconnect of said first active layer and said second interconnect via of said second active layer so that said first pad associated with said metal interconnect of said first active layer is disposed generally opposite to said second pad associated with said second interconnect via of said second active layer; and

coupling said first pad to said second pad to establish an electrical connection from said first interconnect via on said bottom surface of said first active layer to said metal interconnect on said top surface of said second active layer.

7. The method according to claim 3, wherein said joining step includes the steps of:

aligning said metal interconnect of said first active layer and said metal interconnect of said second active layer so that said first pad associated with said metal interconnect of said first active layer is disposed generally opposite to said second pad associated with said metal interconnect of said second active layer; and

coupling said first pad to said second pad to establish an electrical connection from said first interconnect via on said bottom surface of said first active layer to said second interconnect via on said bottom surface of said second active layer.

19. The method according to claim 1, wherein said removing step includes the step of performing an epitaxial etch stop process on one of the first and second active layers.

8. A method for coupling a first active layer of a first semiconductor device to a second active layer of a second semiconductor device, the method comprising the steps of:

forming a first interconnect via on a bottom surface of said first active layer which is electrically and mechanically coupled to a metal interconnect placed on a top surface of said first active layer;

forming a second interconnect via on a second surface of said second active layer which is electrically and mechanically coupled to a metal interconnect placed on a top surface of said first active layer;

visually aligning said first interconnect via of said first active layer and said second interconnect via of said second active layer so that a pad of said first interconnect via of said first active layer is disposed generally opposite to a pad of said second interconnect via of said second active layer, said visually aligning step is accomplished by viewing through a window of insulative material unobscured by the metal interconnect within the first active layer;

applying a Nitride bonding element to one of said pad of said first interconnect via and said pad of said second interconnect via;

joining said pad of said first interconnect via on said bottom surface of said first active layer and said pad of said second interconnect via on said bottom surface of said second active layer to said Nitride bonding element; and

activating said Nitride bonding element to couple said first active layer to said second active layer.

9. A method for creating an electronic device comprising the steps of:

separating a first active layer from a first semiconductor device, said first active layer functioning as a complete integrated circuit and including a field oxide layer, an epitaxy layer partially deposited over and disjoined by the field oxide layer and a metal interconnect partially placed over said field oxide layer and said epitaxy layer allowing for at least one field oxide window to be present;

forming a first interconnect via within said field oxide layer of said first active layer by undergoing a first etching process;

separating a second active layer from a second semiconductor device, said second active layer including a field oxide layer, an epitaxy layer deposited over and disjoined by the field oxide layer and a metal interconnect placed over said field oxide layer and said epitaxy layer;

forming a second interconnect via within said field oxide layer of said second active layer by undergoing a second etching process; and

joining said first active layer and said second active layer by (i) visually aligning a first pad on said first active layer with a second pad on said second active layer by viewing through the at least one field oxide window of the first active layer, and (ii) electrically coupling said first active layer with said second active layer.

10. The method according to claim 9, wherein prior to said step of forming said first interconnect via, the method further comprises the steps of:

testing said first active layer to determine if said first active layer is operational; and

testing said second active layer to determine if said second active layer is operational.

11. The method according to claim 9, wherein said step of forming said first interconnect via includes the steps of

etching said field oxide layer of the first active layer to produce a feedthrough without contacting said epitaxy layer, and

applying metal to said feedthrough to produce said first interconnect via establishing an electrical coupling to said metal interconnect of the first active layer.

12. The method according to claim 11, wherein said step of forming said second interconnect via includes the step of:

etching said field oxide layer of the second active layer to produce a feedthrough without contacting said epitaxy layer, and

applying metal to said feedthrough to produce said second interconnect via establishing an electrical coupling to said metal interconnect of the second active layer.

13. The method according to claim 12, wherein said joining step includes the steps of:

aligning said first interconnect via of said first active layer and said second interconnect via of said second active layer so that said first pad associated with said first interconnect via of said first active layer is disposed generally opposite to said second pad associated with said second interconnect via of said second active layer; and

coupling said first pad to said second pad to establish an electrical connection from said metal interconnect of said first active layer to said metal interconnect of said second active layer.

14. The method according to claim 12, wherein said joining step includes the steps of:

aligning said first interconnect via of said first active layer and said metal interconnect of said second active layer so that said first pad associated with said first interconnect via of said first active layer is disposed generally opposite to said second pad associated with said metal interconnect of said second active layer; and

coupling said first pad to said second pad to establish an electrical connection from said metal interconnect of said first active layer to said second interconnect via of said second active layer.

15. The method according to claim 12, wherein said joining step includes the steps of:

aligning said metal interconnect of said first active layer and said second interconnect via of said second active layer so that said first pad associated with said metal interconnect of said first active layer is disposed generally opposite to said second pad associated with said second interconnect via of said second active layer; and

coupling said first pad to said second pad to establish an electrical connection from said first interconnect via of said first active layer to said metal interconnect of said second active layer.

16. The method according to claim 12, wherein said joining step includes the steps of:

aligning said metal interconnect of said first active layer and said metal interconnect of said second active layer so that said first pad associated with said metal interconnect of said first active layer is disposed generally opposite to said second pad associated with said metal interconnect of said second active layer; and

coupling said first pad to said second pad to establish an electrical connection from said first interconnect via of said first active layer to said second interconnect via of said second active layer.

17. The method according to claim 9, wherein said joining step includes the steps of:

visually aligning said first pad to be disposed generally opposite to said pad of said second interconnect via;

applying a Nitride bonding element to at least one of said first and second pads;

joining said first pad and said second pad with said Nitride bonding element; and

activating said Nitride bonding element to couple said first active layer to said second active layer.

18. The method according to claim 9, wherein at least one of said separating steps includes an epitaxial etch stop process.