Method for manufacturing a low dielectric constant inter-level integrated circuit structure

• US 5,880,018 A
• Filed: 10/07/1996
• Issued: 03/09/1999
• Est. Priority Date: 10/07/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Boeck, Bruce Allen, Wetzel, Jeff Thomas, Sparks, Terry Grant
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US08/727,159
• Time in Patent Office: 883 Days
• Field of Search: 438/619, 438/622, 438/623, 438/627, 438/633, 438/700
• US Class Current: 438/619
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An interconnect structure having a dielectric layer with low dielectric constant is formed within an integrated circuit. In one embodiment of the invention, portions of a silicon dioxide layer (18) lying adjacent to a conductive interconnect (21) are removed to expose portions of a silicon nitride etch stop layer (16). A dielectric layer (22) having a low dielectric constant is then formed overlying the conductive interconnect (21) and the exposed portions of the silicon nitride etch stop layer (16). A portion of the dielectric layer (22) is then removed to expose the top surface of the conductive interconnect (21) to leave portions of the dielectric layer (22) between adjacent conductive interconnects (21). The resulting interconnect structure has reduced cross-talk between conductive interconnects (21) while avoiding prior art disadvantages of reduced thermal dissipation and increased mechanical stress.

Claims

1. An method for forming a semiconductor device, the method comprising the steps of:

forming a first dielectric layer having a first trench region and a second trench region separated from the first trench region;

forming a first conductive region in the first trench region and a second conductive region in the second trench region using a first planarization process, the second conductive region being laterally separated from the first conductive region wherein the first and second conductive regions are separated by an intermediate portion of the first dielectric layer;

removing the intermediate portion of the first dielectric layer to form a gap between the first and second conductive regions;

forming a second dielectric layer having a dielectric constant ε

wherein ε

≦

3.5 overlying the first and second conductive regions, the second dielectric layer having a first portion which fills the gap; and

polishing a top portion of the dielectric layer to expose a top surface of at least one of the first conductive region or the second conductive region wherein the first portion of the second dielectric layer remains within the gap.

2. The method of claim 1 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer as an organic dielectric.

3. The method of claim 1 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer using a spin-on process wherein the second dielectric layer is a spin-on glass layer.

4. The method of claim 1 wherein the step of forming the second dielectric layer comprises:

forming an anti-reflective coating (ARC) over a portion of the second dielectric layer after the step of polishing.

5. The method of claim 1 wherein the step of forming a first conductive region and a second conductive region comprises:

forming an anti-reflective coating (ARC) over a portion of the first conductive region.

6. The method of claim 1 further comprising the step of:

forming an etch stop layer underlying an upper portion of the first conductive region.

7. The method of claim 1 wherein the step of forming a first conductive region and a second conductive region comprises:

forming an refractory metal barrier under the first conductive region.

8. The method of claim 7 wherein the step of forming a first conductive region and a second conductive region comprises:

forming the refractory metal barrier from a material selected from a group consisting of;

titanium nitride, titanium tungsten, titanium, tantalum, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, and tungsten nitride.

9. The method of claim 1 wherein the step of forming a first conductive region and a second conductive region comprises:

forming the first conductive region form a material selected from a group consisting of;

copper, silver, gold, and aluminum.

10. The method of claim 1 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer from a material selected from a group consisting of;

HSQ, BCB, polyimide, and PAE.

11. The method of claim 1 wherein the step of polishing a top portion of the second dielectric layer comprises:

removing a top portion of the second dielectric layer by polishing a top portion of the second dielectric layer using a chemical mechanical polish process.

12. The method of claim 1 wherein the step of polishing a top portion of the second dielectric layer comprises:

removing a top portion of the second dielectric layer by etching away a top portion of the second dielectric layer using an etch chemistry.

13. The method of claim 1 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer having a dielectric constant ε

wherein ε

≦

3.0.

14. The method of claim 1 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer having a dielectric constant ε

wherein ε

≦

2.7.

15. The method of claim 1 wherein the step of forming a first conductive region and a second conductive region comprises:

forming the first conductive region and the second conductive region from a same dual in-laid process step.

16. The method of claim 1 wherein the step of forming a first conductive region and a second conductive region comprises:

forming the first conductive region having a low conductive contact portion and an upper conductive interconnect portion to form an in-laid metal structure.

17. The method of claim 1 further comprising:

removing the intermediate portion of the first dielectric layer using a buffered HF solution.

18. An method for forming a semiconductor device, the method comprising the steps of:

forming a first dielectric layer;

forming contact openings in first dielectric layer;

forming a second dielectric layer overlying the first dielectric layer wherein the second dielectric layer bridges the contact openings to form contact air gaps;

forming openings through the second dielectric layer to expose the contact air gaps and form interconnect trenches; and

forming conductive material within the contact air gaps and the interconnect trenches to form a conductive interconnect wherein conductive material in the interconnect trenches are separated by the second dielectric layer.

19. The method of claim 18 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer as a low dielectric constant material having a dielectric constant ε

wherein ε

≦

3.5.

20. The method of claim 18 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer as a low dielectric constant material having a dielectric constant ε

wherein ε

≦

3.0.

21. The method of claim 18 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer as a low dielectric constant material having a dielectric constant ε

wherein ε

≦

2.7.

22. The method of claim 18 further comprising the step of:

forming a capping layer overlying the conductive material.

23. The method of claim 18 wherein the step of forming a conductive material comprises:

forming an refractory metal barrier under the conductive material.

24. The method of claim 23 wherein the step of forming the conductive material comprises:

forming the refractory metal barrier from a material selected from a group consisting of;

titanium nitride, titanium tungsten, titanium, tantalum, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, and tungsten nitride.

25. The method of claim 18 further comprising:

forming an anti-reflective coating (ARC) layer over a top portion of the second dielectric layer.

26. The method of claim 18 further comprising:

forming an anti-reflective coating (ARC) layer under and in contact with the first dielectric layer.

27. The method of claim 18 wherein the step of forming conductive material further comprises:

forming the conductive material within the interconnects trenches wherein the conductive material within the interconnects trenches has a first width; and

forming the conductive material within the contact air gaps wherein the conductive material within the contact air gaps has a second width, the second width being less than the first width.

28. The method of claim 18 wherein the step of forming a second dielectric layer comprises:

exposing the second dielectric layer to a temperature elevated above room temperature to remove solvents from the second dielectric layer.

29. The method of claim 28 wherein the step of forming a second dielectric layer comprises:

ramping the temperature from a low temperature to a high temperature above 100°

C. at a selected rate wherein the selected rate substantially avoids blistering of the contact air gap.

30. The method of claim 18 wherein the step of forming a second dielectric layer comprises:

forming the second dielectric layer in a sub-atmospheric environment whereby fewer molecules or atoms are trapped within the contact air gaps.

31. The method of claim 18 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer by a spin-on process.

32. The method of claim 31 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric as a PPQ spin-on polymer.

33. The method of claim 31 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer as a spin-on polyimide.

34. The method of claim 31 wherein the step of forming the second dielectric layer comprises:

forming the second dielectric layer as a spin-on polyimide selected from a group consisting of;

poly (amic) acid solution and fully imidized polyimide.

35. An method for forming a semiconductor device, the method comprising the steps of:

forming a plurality of separated conductive members wherein adjacent separated conductive members in the plurality of separated conductive members are separated by gaps; and

forming a first dielectric layer, via a spin-on process, overlying the plurality of separated conductive members whereby at least one of the gaps is bridged by the first dielectric layer to form at least one air region, wherein the at least one air region has a dielectric constant less than 2.0 and improves isolation between at least two separated conductive members in the plurality of separated conductive members wherein the first dielectric layer is selected from a group consisting of;

a spin-on polyimide material, a PPQ spin-on polymer, and a material selected from a group consisting of poly(amic) acid solution and fully imidized polyimide.

36. The method of claim 35 wherein the step of forming a first dielectric layer comprises:

forming the first dielectric layer in a sub-atmospheric environment.

37. The method of claim 35 wherein the step of forming a first dielectric layer comprises:

annealing the first dielectric layer using an anneal process within the temperature range of 100°

C. to 250°

C. after formation of the first dielectric layer.

38. The method of claim 35 further comprising:

forming at least a portion of the plurality of separated conductive members as an inlaid copper interconnect structure.

39. The method of claim 35 further comprising the step of:

forming a second dielectric layer over the plurality of separated conductive members wherein the first dielectric layer is formed overlying the second dielectric layer.

40. The method of claim 39 further comprising the step of:

etching the second dielectric layer to form sidewall spacers laterally adjacent the plurality of separated conductive members.

41. The method of claim 35 wherein the step of forming a first dielectric layer comprises:

forming the first dielectric layer such that the first dielectric layer fills other gaps between the plurality of separated conductive members while not filling in the at least one air region since the other gaps have widths larger than a width of the at least one air region.

42. The method of claim 35 further comprising:

forming a second dielectric layer overlying the first dielectric layer.

43. The method of claim 42 further comprising:

planarizing the second dielectric layer so that the composite layer comprising the first and second dielectric layer made substantially planar.

44. A method for forming an integrated circuit structure comprising the steps of:

providing a semiconductor substrate;

forming a first dielectric layer overlying the semiconductor substrate;

forming a plurality of conductive members overlying the first dielectric layer, wherein the plurality of conductive members are separated by a first distance X;

depositing a nonconformal dielectric layer overlying the plurality of conductive member, wherein the nonconformal dielectric layer is deposited using plasma enhanced chemical vapor deposition and forms a sealed void region between at least two of the conductive members in the plurality of conductive members, the sealed void region spanning at least 50 percent of the first distance X; and

forming a second dielectric layer, the second dielectric layer overlying the sealed void region and the nonconformal dielectric layer.

45. The method of claim 44, wherein the step of depositing the nonconformal dielectric layer, the sealed void region is further characterized as spanning at least 60 percent of the first distance.

46. The method of claim 45, wherein the step of depositing the nonconformal dielectric layer, the sealed void region is further characterized as spanning at least 70 percent of the first distance.

47. The method of claim 46, wherein the step of depositing the nonconformal dielectric layer, the sealed void region is further characterized as spanning at least 80 percent of the first distance.

48. The method of claim 47, wherein the step of depositing the nonconformal dielectric layer, the sealed void region is further characterized as spanning at least 90 percent of the first distance.

49. The method of claim 48, wherein the step of depositing the nonconformal dielectric layer is further characterized as depositing the nonconformal dielectric layer using silane as a source gas.

50. An method for forming a semiconductor device, the method comprising the steps of:

forming a plurality of separated conductive members wherein adjacent separated conductive members in the plurality of separated conductive members are separated by gaps;

forming a second dielectric layer over the plurality of separated conductive members;

etching the second dielectric layer to form sidewall spacers laterally adjacent the plurality of separated conductive members; and

forming a first dielectric layer, via a spin-on process, overlying the second dielectric layer and the plurality of separated conductive member whereby at least one of the gaps is bridged by the first dielectric layer to form at least one air region, wherein the at least one air region has a dielectric constant less than 2.0 and improves isolation between at least two separated conductive members in the plurality of separated conductive members.