Low and high voltage CMOS devices and process for fabricating same

• US 5,880,502 A
• Filed: 09/06/1996
• Issued: 03/09/1999
• Est. Priority Date: 09/06/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Display Technology, Inc. (PixTech, Inc.)
• Inventors: Moradi, Behnam, Lee, John K., Westphal, Michael J.
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US08/709,425
• Time in Patent Office: 914 Days
• Field of Search: 257/369, 257/371, 257/372, 257/389, 257/396, 257/399, 257/400
• US Class Current: 257/372
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

Claims

1. A semiconducting structure comprising:

a substrate;

a gate oxide extending from a first end to a second end, the gate oxide being disposed on the substrate

a first thick field oxide extending from the first end of the gate oxide away from the gate oxide;

a second thick field oxide extending from the second end of the gate oxide away from the gate oxide;

a first p+ doped region disposed under the first thick field oxide;

a second p+ doped region disposed under the second thick field oxide;

a first gate disposed over the gate oxide, a first portion of the first gate extending over a portion of the first thick field oxide and a second portion of the first gate extending over a portion of the second thick field oxide.

2. A semiconducting structure according to claim 1, a first portion of the first p+ doped region being disposed under the first thick field oxide, a second portion of the first p+ doped region being disposed under a portion of the gate oxide.

3. A semiconducting structure according to claim 2, a first portion of the second p+ doped region being disposed under the second thick field oxide, a second portion of the second p+ doped region being disposed under a portion of the gate oxide.

4. A semiconducting structure according to claim 3, a concentration of p+ dopants in the first portion of the first p+ doped region being greater than in the second portion of the first p+ doped region, and a concentration of p+ dopants in the first portion of the second p+ doped region being greater than in the second portion of the second p+ doped region.

5. A semiconducting structure according to claim 1, further comprising an n-well, the first and second p+ doped regions being disposed in the n-well.

6. A semiconducting structure according to claim 5, further including a stop region.

7. A semiconducting structure according to claim 6, wherein the first and second p+ doped regions and the stop region are formed by simultaneously implanting dopants through the first and second thick field oxides into the substrate.

8. A semiconducting structure according to claim 1, further including an nmos transistor comprising:

an active region;

a second gate disposed over at least a portion of the active region;

an n+ doped source region disposed in the substrate under the active region;

an n+ doped drain region disposed in the substrate under the active region.

9. A semiconducting structure according to claim 8, wherein the n+ doped source region, the n+ doped drain region, the first gate, and the second gate are formed by simultaneously implanting n+ type dopants into the device.

10. A semiconducting structure according to claim 1, further including an nmos transistor comprising:

a third thick field oxide;

a second gate oxide disposed on the substrate on one side of the third thick field oxide;

a third gate oxide disposed on the substrate on a side of the third thick field oxide opposite the one side;

an n+ doped source region disposed in the substrate under the second gate oxide;

an n+ doped drain region disposed in the substrate under the third gate oxide;

an n+ doped gate, a portion of the n+ doped gate being disposed over the second gate oxide and a portion of the n+ doped gate being disposed over the third thick field oxide.

11. A semiconducting structure according to claim 10, further including an n- tank disposed in the substrate, the n+ doped drain region being disposed in the n- tank.

12. A semiconducting structure according to claim 11, further including a stop region disposed between the first gate and the nmos transistor.

13. A semiconducting structure according to claim 12, wherein the first and second p+ doped regions and the stop region are fabricated by simultaneously implanting dopants into the structure.

14. A semiconducting structure according to claim 13, further including a pmos transistor including:

a fourth thick field oxide;

a p+ doped source region disposed under the fourth thick field oxide;

a p+ doped drain region disposed under the fourth thick field oxide;

a second gate disposed over the fourth thick field oxide.