IC having memoried terminals and zero-delay boundary scan

• US 5,880,595 A
• Filed: 04/11/1997
• Issued: 03/09/1999
• Est. Priority Date: 04/28/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/827,844
• Time in Patent Office: 697 Days
• Field of Search: 326/16, 326/39-41, 326/47, 371/22.2, 371/22.3, 371/22.31, 371/22.32
• US Class Current: 326/16
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

An electronic integrated circuit includes a signal path for carrying a functional signal between functional logic (15) and an external terminal, which signal path includes a memory element (121, 123, 127). When a test signal is applied to the signal path, a switch (S) of the memory element isolates the test signal from the functional signal.

Claims

1. An electronic integrated circuit, comprising:

A. functional core logic;

B. a terminal accessible externally of the integrated circuit;

C. a signal path connected between the functional logic and the terminal for carrying a functional signal;

D. a latch circuit having an input and an output and having at least two portions connected in series in the signal path; and

E. a serial scan path including;

i. a serial input lead,

ii. a multiplexer circuit having an output, a first input connected to the serial input lead and a second input connected to the signal path at one of the input and output of the latch circuit,

iii. a serial output lead,

iv. a memory circuit having an input connected to the output of the multiplexer circuit and an output connected to the serial output lead, and

v. a test switch connected between the serial output lead and the signal path between the two portions of the latch circuit.

2. The circuit of claim 1 in which one portion of the latch circuit is a latching buffer circuit having an input and an output and the other portion of the latch circuit is a functional switch.

3. The circuit of claim 2 in which the latching buffer circuit is an output buffer, the buffer input connects to the functional switch and the buffer output connects to the terminal.

4. The circuit of claim 2 in which the latching buffer circuit is an input buffer, the buffer input connects to the functional switch and the buffer output connects to the functional core logic.

5. The circuit of claim 2 in which the latching buffer circuit includes a main buffer circuit and a feedback circuit from the main buffer circuit output to the main buffer circuit input.

6. The circuit of claim 5 in which the feedback circuit is a buffer circuit weaker than the main buffer circuit.

7. The circuit of claim 5 in which the feedback circuit includes an enable input.

8. The circuit of claim 7 including a mode circuit having an output connected to the enable input and having a first input connected to an enable signal and a second input connected to a ground signal.

9. The circuit of claim 1 in which the multiplexer circuit includes a third input connected to the signal path between the portions of the latch circuit.

10. The circuit of claim 1 in which the multiplexer circuit includes a third input connected to the signal path between the functional core logic and the latch circuit.

11. The circuit of claim 1 including a bus holder circuit connected to the signal path between the two portions of the latch circuit.

12. The circuit of claim 1 including:

i. a control signal path between the functional core logic and the latch circuit;

ii. one portion of the latch circuit is a latching buffer circuit having a tristate output and having a control input connected to the control signal path;

iii. a control switch in the control signal path between the functional core logic and latch circuit; and

iv. the serial scan path includes;

a. a second multiplexer circuit having an output, a first input connected to the serial output lead and a second input connected to the control signal path between the functional core logic and the control switch,

b. a second serial output lead,

c. a second memory circuit having an input connected to the output of the multiplexer circuit and an output connected to the second serial output lead, and

d. a second test switch connected between the second serial output lead and the control signal path between the control switch and the control input of the latch circuit.

13. The circuit of claim 12 including a bus holding circuit connected to the control signal path between the control switch and the latch circuit.