Tile-based modular routing resources for high density programmable logic device

• US 5,880,598 A
• Filed: 01/10/1997
• Issued: 03/09/1999
• Est. Priority Date: 01/10/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Duong, Khue
• Primary Examiner(s): Tokar, Michael J.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/781,251
• Time in Patent Office: 788 Days
• Field of Search: 326/39, 326/41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs. A corner tile is also provided that permits interconnection between horizontal and vertical tiles. The tiles are modular in nature so the number of tiles provided within an array and their placement are determined based on the array'"'"'s particular need for routing resources, e.g., an array can have one, two or more tiles associated with a row or column of CLBs in areas of the chip where congestion is typically encountered. Each tile of the present invention can also include a plurality of switch matrices, buffers, or other active gates to facilitate signal routing.

Claims

1. A semiconductor device having an array of configurable logic blocks each having programmable logic elements and programmable routing resources, said semiconductor device comprising:

a first plurality of coupled modular routing resource tiles having a plurality of conductive segments for coupling to a first set of configurable logic blocks, each of said first plurality of modular routing resource tiles positioned proximate to a first edge of a corresponding one of said configurable logic blocks of said first set, said first plurality of tiles having programmable circuitry for selectively coupling to the routing resources of said configurable logic blocks of said first set;

a second plurality of coupled modular routing resource tiles having a plurality of conductive segments for coupling to a second set of configurable logic blocks, each of said second plurality of modular routing resource tiles positioned proximate to a second edge of a corresponding one of said configurable logic blocks of said second set, said second plurality of tiles having programmable circuitry for selectively coupling to the routing resources of said configurable logic blocks of said second set; and

interconnecting circuitry for interconnecting said first and second modular routing resource tiles.

2. The semiconductor device of claim 1 further comprising:

a first input/output block located on a first edge of said device; and

a second input/output block located on a second edge of said device, wherein said first plurality of coupled modular routing resource tiles provide a modular communication pathway between said first input/output block and said second input/output block.

3. The semiconductor device of claim 1 further comprising:

a first input/output block located on a first edge of said device; and

a second input/output block located on said first edge of said device, wherein said first plurality of coupled modular routing resource tiles provide a modular communication pathway between said first input/output block and said second input/output block.

4. The semiconductor device of claim 1 wherein said configurable logic blocks of said first and second set are generally rectangular in boundary, said first edge of each configurable logic block comprises a vertical edge of said boundary and said second edge of each configurable logic block comprises a horizontal edge of said boundary.

5. The semiconductor device of claim 4 wherein said first plurality of modular routing resource tiles comprise:

vertical modular tiles each having a plurality of vertical long line segments and a plurality of vertical quad line segments; and

programmable circuitry for coupling each of said plurality of vertical long line and quad line segments to individual segments of a plurality of horizontal line segments, said plurality of horizontal line segments being part of the routing resources within a configurable logic block.

6. The semiconductor device of claim 4 wherein said second plurality of modular routing resource tiles comprise:

horizontal modular tiles each having a plurality of horizontal long line segments and a plurality of horizontal quad line segments; and

programmable circuitry for coupling each of said plurality of horizontal long line and quad line segments to individual segments of a plurality of vertical line segments, said plurality of vertical line segments being part of the routing resources within a configurable logic block.

7. The semiconductor device of claim 4 wherein said interconnecting circuitry comprises a modular corner tile having:

first circuitry for connecting vertical long line segments of a first modular vertical tile to corresponding vertical long line segments of an adjacent second modular vertical tile;

second circuitry for connecting vertical quad line segments of said first modular vertical tile to corresponding vertical quad line segments of said adjacent second modular vertical tile;

third circuitry for connecting horizontal long line segments of a first modular horizontal tile to corresponding horizontal long line segments of an adjacent second modular horizontal tile; and

fourth circuitry for connecting horizontal quad line segments of said first modular horizontal tile to corresponding horizontal quad line segments of said adjacent second modular horizontal tile.

8. The semiconductor device of claim 7 wherein said interconnecting circuitry further comprises a plurality of programmable interconnects for coupling individual vertical long line and quad line segments of a modular vertical tile to one or ones of said horizontal long line and quad line segments of a modular horizontal tile.

9. A field programmable gate array integrated circuit device comprising:

a plurality of configurable logic blocks each comprising;

programmable logic elements for implementing logic functions;

a programmable interconnect structure of horizontal and vertical signal lines; and

at least one switch matrix for interconnecting individual signal lines of said horizontal and vertical signal lines; and

a plurality of intercoupled modular routing resource tiles each comprising a plurality of conductive segments and programmable circuitry coupled thereto for selectively coupling said plurality of conductive segments to individual signal lines of said horizontal and vertical signal lines, said plurality of modular routing resource tiles coupled together and disposed in areas of said field programmable gate array expected to have routing resource congestion attributed to dense concentrations of said configurable logic blocks.

10. The field programmable gate array integrated circuit device of claim 9 wherein said programmable circuitry comprise:

programmable buffers;

programmable six-transistors matrices; and

programmable interconnect point circuits.

11. The field programmable gate array integrated circuit device of claim 9 wherein said plurality of modular routing resource tiles comprise:

a plurality of intercoupled modular vertical tiles providing additional routing resources in a vertical direction across said array;

a plurality of intercoupled modular horizontal tiles providing additional routing resources in a horizontal direction across said array; and

a plurality of modular corner tiles, said modular corner tiles for programmably coupling routing resources of said modular vertical tiles with said routing resources of said modular horizontal tiles.

12. The field programmable gate array integrated circuit device of claim 11 wherein said modular corner tiles further comprise:

first circuitry for interconnecting one of said plurality of vertical tiles to another proximate vertical tile to form a contiguous conductor having a length longer than the length of two configurable logic blocks; and

second circuitry for interconnecting one of said plurality of horizontal tiles to another proximate horizontal tile to form a contiguous conductor having a length longer than the length of two configurable logic blocks.

13. A field programmable gate array integrated circuit device comprising:

a plurality of configurable logic blocks each comprising;

programmable logic elements for implementing logic functions;

a programmable interconnect structure of horizontal and vertical signal lines; and

at least one switch matrix for interconnecting individual signal lines of said horizontal and vertical signal lines; and

a plurality of horizontal modular routing resource tiles each comprising a plurality of conductive segments and programmable circuitry coupled thereto for selectively coupling said plurality of conductive segments to individual signal lines of said vertical signal lines of said configurable logic blocks;

a plurality of vertical modular routing resource tiles each comprising a plurality of conductive segments and programmable circuitry coupled thereto for selectively coupling said plurality of conductive segments to individual signal lines of said horizontal signal lines of said configurable logic blocks; and

a plurality of corner modular routing resource tiles for coupling individual horizontal modular routing resource tiles to one another to form horizontal lines, for coupling individual vertical modular routing resource tiles to one another to form vertical lines, and for coupling individual vertical modular routing resource tiles to individual horizontal modular routing resource tiles.

14. The field programmable gate array integrated circuit device of claim 13 wherein said programmable circuitry of said horizontal and vertical modular routing resource tiles comprise programmable buffers.

15. The field programmable gate array integrated circuit device of claim 13 wherein said programmable circuitry of said horizontal and vertical modular routing resource tiles comprise programmable six-transistors matrices.

16. The field programmable gate array integrated circuit device of claim 13 wherein said programmable circuitry of said horizontal and vertical modular routing resource tiles comprise programmable interconnect point circuits.

17. The field programmable gate array integrated circuit device of claim 16 wherein said modular corner routing resource tiles comprise:

first circuitry for interconnecting one of said plurality of vertical modular routing resource tiles to another proximate vertical modular routing resource tile to form a contiguous conductor having a length longer than the length of two configurable logic blocks; and

second circuitry for interconnecting one of said plurality of horizontal modular routing resource tiles to another proximate horizontal modular routing resource tile to form a contiguous conductor having a length longer than the length of two configurable logic blocks.

18. The field programmable gate array integrated circuit device of claim 13 wherein said plurality of conductive segments of said horizontal and vertical modular routing resource tiles comprise:

substantially parallel long line conductive segments; and

quad line conductive segments having a programmable bi-directional buffer coupled to one of said quad line conductive segments for buffering each quad line conductive segments once every four coupled tiles.

19. The field programmable gate array integrated circuit device of claim 18 wherein said programmable circuitry of said horizontal and vertical modular routing resource tiles comprise programmable six-transistors matrices coupled to said quad line conductive segments and programmable interconnect point circuits coupled to said quad line conductive segments.

20. The field programmable gate array integrated circuit device of claim 18 wherein said programmable circuitry of said horizontal and vertical modular routing resource tiles comprise programmable buffers coupled to long line conductive segments.

21. A method for increasing the routing resources of a field programmable gate array integrated circuit device, said method comprising the steps of:

a) placing a plurality of configurable logic blocks in a plurality of rows and columns of an array, each of said configurable logic blocks having programmable logic elements and programmable routing resources;

b) placing a plurality of modular vertical routing resource tiles between selected columns of said plurality of columns of configurable logic blocks;

c) placing a plurality of modular horizontal routing resource tiles between selected rows of said plurality of rows of configurable logic blocks; and

d) placing a plurality of modular corner tiles at intersections of said plurality of vertical routing resource tiles and said plurality of horizontal routing resource tiles, such that said plurality of modular horizontal, vertical and corner tiles are disposed within areas of said array to relieve routing resource congestion.

22. A method as described in claim 21 wherein said steps b), c) and d) dispose vertical and horizontal routing resource tiles within the central portion and the periphery of said field programmable gate array.

23. A semiconductor device having an array of configurable logic blocks each having programmable logic elements and programmable routing resources, said semiconductor device comprising:

a first plurality of coupled modular routing resource tiles having a plurality of conductive segments for coupling to a first set of configurable logic blocks, each of said first plurality of modular routing resource tiles positioned proximate to a first edge of a corresponding one of said configurable logic blocks of said first set, said first plurality of tiles having programmable circuitry for selectively coupling to the routing resources of said configurable logic blocks of said first set.