Pass gate circuit with body bias control

• US 5,880,620 A
• Filed: 04/22/1997
• Issued: 03/09/1999
• Est. Priority Date: 04/22/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Voogel, Martin L., Gitlin, Daniel, Zhao, Tiemin, Li, Sheau-Suey
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US08/840,582
• Time in Patent Office: 686 Days
• Field of Search: 326/98, 327/388, 327/434, 327/534-535
• US Class Current: 327/534
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.

Claims

1. A pass gate circuit comprising:

a pass transistor including a gate, a first terminal and a body; and

a body bias control circuit connected between the first terminal, the gate and the body;

wherein the body bias control circuit is controlled by one of the first terminal and the gate to selectively connect the body to one of the first terminal and the gate when one of the first terminal and the gate are at predetermined voltage levels.

2. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal and a gate connected to the gate of the pass transistor, the first control transistor also having a second terminal; and

a second control transistor having a first terminal connected to the second terminal of the first control transistor, a gate connected to the first terminal of the pass transistor, and a second terminal connected to the body of the pass transistor.

3. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a control transistor having a first terminal connected to the gate of the pass transistor, a second terminal connected to the body of the pass transistor, and a gate connected to the first terminal of the pass transistor.

4. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a control transistor having a first terminal connected to the first terminal of the pass transistor, a second terminal connected to the body of the pass transistor, and a gate connected to the gate of the pass transistor.

5. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the first terminal of the pass transistor, a second terminal connected to the body of the pass transistor, and a gate connected to the gate of the pass transistor; and

a second control transistor having a first terminal connected to the gate of the pass transistor, a gate connected to the first terminal of the pass transistor, and a second terminal connected to the body of the pass transistor.

6. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the gate of the pass transistor, a second terminal connected to the body of the pass transistor, and a gate connected to the first terminal of the pass transistor; and

a second control transistor having a first terminal connected to the gate of the pass transistor, a gate connected to a second terminal of the pass transistor, and a second terminal connected to the body of the pass transistor.

7. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the gate of the pass transistor, a second terminal connected to the body of the pass transistor, and a gate connected to the first terminal of the pass transistor;

a second control transistor having a first terminal connected to the gate of the pass transistor, a gate connected to a second terminal of the pass transistor, and a second terminal connected to the body of the pass transistor; and

a third control transistor having a first terminal connected to the first terminal of the pass transistor, a second terminal connected to the body of the pass transistor, and a gate connected to the gate of the pass transistor.

8. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the gate of the pass transistor, a gate connected to the first terminal of the pass transistor, and a second terminal connected the body of the pass transistor; and

a second control transistor having a first terminal connected to the second terminal of the first control transistor and the body of the pass transistor, a gate, and a second terminal connected to ground;

wherein the gate of the second control transistor is controlled by a first signal, and the first terminal of the pass transistor receives a second signal, and

wherein the first signal is a logical inverse of the second signal.

9. The pass gate circuit according to claim 8, further comprising an inverter, wherein the gate of the second control transistor is connected to an input terminal of the inverter, and the first terminal of the pass transistor is connected to an output terminal of the inverter.

10. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the first terminal of the pass transistor, a gate connected to the gate of the pass transistor, and a second terminal connected the body of the pass transistor; and

a second control transistor having a first terminal connected to the second terminal of the first control transistor and to the body of the pass transistor, a gate, and a second terminal connected to ground;

wherein the gate of the second control transistor is controlled by a first signal, and the first terminal of the pass transistor receives a second signal, and

wherein the first signal is a logical inverse of the second signal.

11. The pass gate circuit according to claim 10, further comprising an inverter, wherein the gate of the second control transistor is connected to an input terminal of the inverter, and the first terminal of the pass transistor is connected to an output terminal of the inverter.

12. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the first terminal of the pass transistor, a gate connected to the gate of the pass transistor, and a second terminal connected to the body of the pass transistor; and

a second control transistor having a first terminal connected to the body of the pass transistor, a second terminal connected to ground, and a gate connected to the gate of the pass transistor.

13. The pass gate circuit according to claim 12, wherein the first control transistor is an NMOS transistor, and the second control transistor is a PMOS transistor.

14. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the gate of the pass transistor, a gate connected to the first terminal of the pass transistor, and a second terminal connected to the body of the pass transistor; and

a second control transistor having a first terminal connected to the body of the pass transistor, a second terminal connected to ground, and a gate connected to the gate of the pass transistor.

15. The pass gate circuit according to claim 14, wherein the first control transistor is an NMOS transistor, and the second control transistor is a PMOS transistor.

16. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the first terminal of the pass transistor, a gate connected to the gate of the pass transistor, and a second terminal connected to the body of the pass transistor; and

a second control transistor having a first terminal connected to ground, a gate, and a second terminal connected to the body of the pass transistor;

wherein the gate of the second control transistor is controlled by a first signal, and the gate of the pass transistor receives a second signal, and

wherein the first signal is a logical inverse of the second signal.

17. The pass gate circuit according to claim 16, further comprising an inverter, wherein the gate of the second control transistor is connected to an input terminal of the inverter, and the gate of the pass transistor is connected to an output terminal of the inverter.

18. The pass gate circuit according to claim 17, wherein the inverter is incorporated into an SRAM cell.

19. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises:

a first control transistor having a first terminal connected to the gate of the pass transistor, a gate connected to the first terminal of the pass transistor, and a second terminal connected to the body of the pass transistor; and

a second control transistor having a first terminal connected to ground, a gate, and a second terminal connected to the body of the pass transistor;

wherein the gate of the second control transistor is controlled by a first signal, and the gate of the pass transistor receives a second signal, and

wherein the first signal is a logical inverse of the second signal.

20. The pass gate circuit according to claim 19, further comprising an inverter, wherein the gate of the second control transistor is connected to an input terminal of the inverter, and the gate of the pass transistor is connected to an output terminal of the inverter.

21. The pass gate circuit according to claim 20, wherein the inverter is incorporated into an SRAM cell.

22. The pass gate circuit according to claim 1, wherein the body bias control circuit comprises a control transistor which is formed in a common well region with the pass transistor such that a body of the control transistor is electrically connected to the body of the pass transistor.