Constant potential generating circuit and semiconductor device using same

• US 5,880,624 A
• Filed: 07/07/1995
• Issued: 03/09/1999
• Est. Priority Date: 07/08/1994
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hataoka, Kazuhiro, Koyanagi, Masaru
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US08/499,514
• Time in Patent Office: 1,341 Days
• Field of Search: 326/21, 326/26, 326/27, 326/31, 326/34, 326/82, 326/83, 326/87, 326/89, 326/91, 327/108, 327/112, 327/379, 327/384, 327/389, 327/391, 327/77, 327/87, 327/89, 327/538, 327/540, 327/543, 327/541, 323/313, 323/315, 323/316, 323/317
• US Class Current: 327/541
• CPC Class Codes: H03K 17/167 using parallel switching arrangements

Abstract

When an intermediate potential is required inside a semiconductor device, the constant potential generating circuit can output a stable potential, while maintaining a high driving capability, so that the controllability of the semiconductor device can be improved. The constant potential generating circuit comprises a first output circuit composed of two transistors P16 and N16 for supplying an intermediate output potential V_out to a load; a second output circuit composed of two transistors P11 and N11 for outputting a voltage corresponding to the output potential V_out to a node 13; a resistor R11 interposed between an output point of the output potential V_out and the node 13; and a differential amplifier circuit Ad for comparing the voltage at the node 13 with the reference potential V_ref to apply control signals to the transistors P11, N11, P16 and N16, respectively. In response to the control signals applied from the differential amplifier circuit Ad, the response speed of the second circuit composed of the transistors P11 and N11 is determined higher than that of the first circuit composed of the transistors P16 and N16. Therefore, when the output potential V_out changes relative to the reference potential V_ref, the gate control signals are outputted from the differential amplifier circuit Ad, by comparing the voltage at the node 13 (at which the response speed is high in response to the control signals) with the reference potential V_ref, so that the output potential V_out can be controlled at a stable point at high speed. FIG. 1!

Claims

1. A constant potential generating circuit, comprising:

a first output circuit for outputting an output voltage corresponding to an inputted control signal level, from a first output terminal;

a second output circuit for outputting a comparison voltage corresponding to the inputted control signal level, from a second output terminal at a response speed higher than that of said first output circuit;

a connecting circuit connected between the first output terminal and the second output terminal;

a reference voltage generating circuit for independently generating a reference voltage regardless of the outputs of the first and second output circuits; and

a comparing circuit for comparing the comparison voltage with the reference voltage, outputting the control signal on the basis of the comparison result, controlling the comparison voltage on the basis of the control signal, and further controlling the output voltage by comparing the controlled comparison voltage with the reference voltage.

2. The constant potential generating circuit of claim 1, wherein:

said first output circuit comprises a first transistor and a second transistor both connected in series between a pair of reference supply voltages, an intermediate junction point between said first and second transistors being the first output terminal;

said second output circuit comprises a third transistor and a fourth transistor both connected in series between a pair of the reference supply voltages, an intermediate junction point between said third and fourth transistors being the second output terminal; and

said comparing circuit outputs a first control signal and a second control signal as the control signals and has a first control signal output terminal for outputting the first control signal and a second control signal output terminal for outputting the second control signal, the first control signal output terminal being connected to control terminals of said first and third transistors and the second control signal output terminal being connected to control terminals of said second and fourth transistors.

3. The constant potential generating circuit of claim 1, wherein said connecting circuit comprises a resistance connected in series between the first output terminal and the second output terminal.

4. The constant potential generating circuit of claim 2, wherein said connecting circuit comprises a resistance connected in series between the first output terminal and the second output terminal.

5. The constant potential generating circuit of claim 2, wherein said connecting circuit is a transistor having a control terminal connected to the first control signal output terminal.

6. The constant potential generating circuit of claim 2, wherein said connecting circuit is a transistor having a control terminal connected to the second control signal output terminal.

7. The constant potential generating circuit of claim 2, wherein said connecting circuit is formed by connecting a pair of transistors of different types in parallel to each other;

a control terminal of one of the transistors is connected to the first control signal output terminal; and

a control terminal of the other of the transistors is connected to the second control signal output terminal.

8. The constant potential generating circuit of claim 2, wherein said connecting circuit is a transistor;

the first control signal output terminal is connected to one input terminal of a NOR circuit via an inverter;

the second control signal output terminal is connected to the other input terminal of the NOR circuit;

an output terminal of said NOR circuit is connected to a control terminal of said transistor.

9. The constant potential generating circuit of claim 2, wherein said connecting circuit is a transistor;

the second control signal output terminal is connected to one input terminal of a NAND circuit via an inverter;

the first control signal output terminal is connected to the other input terminal of the NAND circuit; and

an output terminal of said NAND circuit is connected to a control terminal of said transistor.

10. The constant potential generating circuit of claim 2, wherein said connecting circuit is formed by connecting a pair of transistors of different types in parallel to each other;

the first control signal output terminal is connected to one input terminal of a NOR circuit via an inverter;

the second control signal output terminal is connected to the other input terminal of the NOR circuit;

an output terminal of said NOR circuit is connected to a control terminal of one of said transistors;

the second control signal output terminal is connected to one of the input terminals of a NAND circuit via an inverter;

the first control signal output terminal is connected to the other input terminal of said NAND circuit; and

an output terminal of said NAND circuit is connected to a control terminal of the other of said transistors.

11. A semiconductor device, comprising:

first and second MOS transistors connected in series between a supply potential application node and an output node;

a data output control circuit connected to a gate of said second MOS transistor, for driving and controlling said second MOS transistor according to output data;

a reference potential generating circuit for outputting a reference potential changing according to the supply potential; and

an amplifier circuit responsive to the reference potential, for driving and controlling a gate of said first MOS transistor at a potential roughly equal to the reference potential,

wherein said amplifier includes;

a first driving circuit having an output node connected to a gate of said first MOS transistor;

a second driving circuit having an output node connected to an output node of said first driving circuit via a resistance element and operative at a response speed higher than that of said first driving circuit; and

a differential amplifier circuit for comparing an output node potential of said second driving circuit with the reference potential, to control said first and second driving circuits.

12. A semiconductor device, comprising:

first and second MOS transistors connected in series between a supply potential application node and an output node;

a data output control circuit connected to a gate of said second MOS transistor, for driving and controlling said second MOS transistor according to output data;

a reference potential generating circuit for outputting a reference potential changing according to the supply potential; and

an amplifier circuit responsive to the reference potential, for driving and controlling a gate of said first MOS transistor at a potential roughly equal to the reference potential,

said amplifier including;

a first driving circuit having an output node connected to a gate of said first MOS transistor;

a second driving circuit having an output node connected to an output node of said first driving circuit via a switching circuit and operative at a response speed higher than that of said first driving circuit; and

a differential amplifier circuit for comparing an output node potential of said second driving circuit with the reference potential, to control said first and second driving circuits and the switching circuit.

13. A semiconductor device, comprising:

a reference voltage generating circuit for generating a reference voltage changing according to a supply potential;

a first driving circuit having an output node;

a second driving circuit having an output node connected to the output node of said first driving circuit via a resistance element and operative at a response speed higher than that of said first driving circuit;

a differential amplifier circuit for comparing an output node potential of said second driving circuit with the reference potential, to control said first and second driving circuits;

a control signal generating circuit for generating a control signal according to a desired output data level;

a first output circuit connected between an output node of said first driving circuit and said control signal generating circuit, and operative only at a low supply voltage; and

a second output circuit connected to said control signal generating circuit, and operative irrespective of the supply voltage value.

14. A semiconductor device, comprising:

a reference voltage generating circuit for generating a reference voltage changing according to a supply potential;

a first driving circuit having an output node;

a second driving circuit having an output node connected to the output node of said first driving circuit via a switching circuit and operative at a response speed higher than that of said first driving circuit;

a differential amplifier circuit for comparing an output node potential of said second driving circuit with the reference potential, to control said first and second driving circuits and the switch circuit;

a control signal generating circuit for generating a control signal according to a desired output data level;

a first output circuit connected between an output node of said first driving circuit and said control signal generating circuit, and operative only at a low supply voltage; and

a second output circuit connected to said control signal generating circuit, and operative irrespective of the supply voltage value.

15. A semiconductor device, comprising:

a first drive circuit having an output node which outputs a first output;

a second driving circuit having a second output node which outputs a second output connected to the first output node of said first driving circuit via a resistance element and operative at a response speed higher than that of said first driving circuit;

a reference potential generating circuit for independently generating a reference potential regardless of the first and second outputs; and

a differential amplifier circuit for comparing a second output node potential of said second driving circuit with the reference potential, to control said first and second driving circuits;

the first output node of said first driving circuit being driven at roughly the same level as the reference potential.

16. A semiconductor device, comprising:

a first driving circuit having a first output node which outputs a first output;

a second driving circuit having a second output node which outputs a second output connected to the first output node of said first driving circuit via a switching circuit and operative at a response speed higher than that of said first driving circuit;

a reference potential generating circuit for independently generating a reference potential regardless of the first and second outputs; and

a differential amplifier circuit for comparing a second output node potential of said second driving circuit with the reference potential, to control said first and second driving circuits the switching circuit;

the first output node of said first driving circuit being driven at roughly the same level as the reference potential.

17. A semiconductor device, comprising:

a first P-channel MOS transistor connected between a first voltage supply terminal and an output terminal;

a first N-channel MOS transistor connected between a second voltage supply terminal and the output terminal;

a second P-channel MOS transistor connected between the first voltage supply terminal and a comparison terminal;

a second N-channel MOS transistor connected between the second voltage supply terminal and the comparison terminal;

a resistance element connected between the output terminal and the comparison terminal;

a reference potential generating circuit for generating a reference potential;

a comparing circuit for comparing the reference potential with a potential at the comparison terminal and outputting a comparison result;

a first buffer circuit responsive to the comparison result, for driving both said first P-channel MOS transistor and said second P-channel MOS transistor; and

a second buffer circuit responsive to the comparison result, for driving both said first N-channel MOS transistor and said second N-channel MOS transistor, a threshold of said second buffer circuit being different from that of said first buffer circuit.

19. The semiconductor device of claim 17, wherein, the first buffer circuit includes a 1st inverter INV₁ with a threshold voltage of V_th (IVN₁) and the second buffer circuit includes a 2nd inverter INV₂ with a threshold voltage of V_th (IVN₂) and wherein the following equation is satisfied:

space="preserve" listing-type="equation">V.sub.th (INV.sub.1)>

V.sub.th (INV.sub.2).

20.

18. A semiconductor device, comprising:

a first P-channel MOS transistor connected between a first voltage supply terminal and an output terminal;

a first N-channel MOS transistor connected between a second voltage supply terminal and the output terminal;

a second P-channel MOS transistor connected between the first voltage supply terminal and a comparison terminal;

a second N-channel MOS transistor connected between the second voltage supply terminal and the comparison terminal;

a reference potential generating circuit for generating a reference potential;

a comparing circuit for comparing the reference potential with a potential at the comparison terminal and outputting a comparison result;

a first buffer circuit responsive to the comparison result, for driving both said first P-channel MOS transistor and said second P-channel MOS transistor;

a second buffer circuit responsive to the comparison result, for driving both said first N-channel MOS transistor and said second N-channel MOS transistor, a threshold of said second buffer circuit being different from that of said first buffer circuit; and

a switching element connected between the output terminal and the comparison terminal and controlled on the basis of the comparison result.

20. The semiconductor device of claim 18, wherein, the first buffer circuit includes a 1st inverter INV₁ with a threshold voltage of V_th (INV₁) and the second buffer circuit includes a 2nd inverter INV₂ with a threshold voltage of V_th (INV₂) and wherein the following equation is satisfied:

space="preserve" listing-type="equation">V.sub.th (INV.sub.1)>

V.sub.th (INV.sub.2).

21.

21. A semiconductor device, comprising:

a first P-channel MOS transistor connected between a first voltage supply terminal and an output terminal;

a first N-channel MOS transistor connected between a second voltage supply terminal and the output terminal;

a reference potential generating circuit for generating a reference potential;

a comparing circuit having a comparison terminal and an output terminal for comparing the reference potential with a potential at the comparison terminal and outputting a comparison result at the output terminal;

a first buffer circuit including a 1st inverter INV₁ having the threshold voltage of V_th (INV₁), responsive to the comparison result, for driving said first P-channel MOS transistor; and

a second buffer circuit including a 2nd inverter INV₂ having the threshold voltage of V_th (INV₂), responsive to the comparison result, for driving said first N-channel MOS transistor,

wherein the following equation is satisfied;

space="preserve" listing-type="equation">V.sub.th (INV.sub.1)>

V.sub.th (INV.sub.2).