Surface mount multilayer capacitor

• US 5,880,925 A
• Filed: 06/27/1997
• Issued: 03/09/1999
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: AVX Corporation (Kyocera Corporation)
• Original Assignee: AVX Corporation (Kyocera Corporation)
• Inventors: Galvagni, John L., Ritter, Andrew P., DuPre, David A.
• Primary Examiner(s): Kincaid, Kristine
• Assistant Examiner(s): Dinkins, Anthony
• Application Number:
  US08/884,597
• Time in Patent Office: 620 Days
• Field of Search: 361/303-305, 361/306.1-306.3, 361/308.1, 361/310-313, 361/321.1, 361/321.5, 361/301.4, 361/309, 361/322, 361/329
• US Class Current: 361/303
• CPC Class Codes: H01G 2/065 for surface mounting, e.g. chip capacitors
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/09381 Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
• CPC Class Codes: H05K 2201/09663 Divided layout, i.e. conductors divided in two or more parts
• CPC Class Codes: H05K 2201/0979 Redundant conductors or connections, i.e. more than one current path between two points
• CPC Class Codes: H05K 2201/10045 Mounted network component having plural terminals
• CPC Class Codes: H05K 2201/10636 Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: H05K 3/3442 having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A multilayer ceramic device suitable for use in surface mount decoupling applications may have a single capacitor or a capacitor array. The device has a capacitor body defining a plurality of electrical terminals on an outer surface thereof. The terminals are interdigitated such that a respective first polarity terminal will be adjacent to a respective second polarity terminal (and vice versa). The capacitor body contains a plurality of interleaved capacitor plates in opposed and spaced apart relation. Capacitor plates of the first polarity are electrically connected to respective first polarity terminals via a plurality of lead structures. Likewise, a plurality of lead structures electrically connect capacitor plates of the second polarity to respective second polarity terminals.

Claims

1. A multilayer capacitor device suitable for use as a surface mount decoupling capacitor, said multilayer capacitor device comprising:

a low-aspect capacitor body including a plurality of first and second electrode plates interleaved in opposed and spaced apart relation;

a dielectric material located between each opposing set of said first and second electrode plates to provide a predetermined dielectric constant;

said first and second electrode plates each including a main electrode portion and at least two spaced apart lead structures extending therefrom, respective lead structures of said first electrode plates being located adjacent respective lead structures of said second electrode plates in an interdigitated arrangement; and

at least four electrical terminals located on an outer surface of said capacitor body, corresponding lead structures of said first electrode plates and corresponding lead structures of said second electrode plates being electrically connected together by respective ones of said terminals to define a plurality of electrical terminals of a first polarity and a plurality of electrical terminals of a second polarity, respectively, located on said capacitor body.

2. A multilayer capacitor device as set forth in claim 1, wherein said low-aspect capacitor body has an aspect ratio of no more than 0.5:

1.

3. A multilayer capacitor device as set forth in claim 1, wherein said at least four electrical terminals are formed by a thick-film terminal material.

4. A multilayer capacitor device as set forth in claim 1, wherein respective lateral sides of said main electrode portions each have an equal number of said lead structures extending therefrom.

5. A multilayer capacitor device as set forth in claim 4, wherein said main electrode portion of each first electrode plate has a first single lead structure extending from one end side thereof and said main electrode portion of each second electrode plate has a second single lead structure extending therefrom.

6. A multilayer capacitor device as set forth in claim 4, wherein each of said lateral sides has a total of two of said lead structures extending therefrom.

7. A multilayer capacitor device as set forth in claim 4, wherein respective ones of said lead structures extending from one of said lateral sides are offset by one terminal position in relation to respective ones of said lead structures extending from an opposite of said lateral sides.

8. A multilayer capacitor device as set forth in claim 1, wherein said dielectric material located between each opposing set of said first and second electrode plates is a predetermined ceramic dielectric material.

9. A multilayer capacitor device as set forth in claim 8, wherein said capacitor body has a unitary structure characteristic of a plurality of stacked, pressed and sintered ceramic-electrode layers.

10. An electrical circuit arrangement comprising:

a generally planar circuit board having a plurality of electrical current paths defined thereon; and

a capacitor device having a capacitor body surface-mounted on said circuit board and having at least four electrical terminals thereon, said terminals being in respective electrical communication with predetermined ones of said current paths, said capacitor body including;

(a) at least one first electrode plate having a generally rectangular first main electrode portion with a plurality of first lead structures extending therefrom;

(b) at least one second electrode plate situated in opposed and spaced apart relation to said first electrode plate, said second electrode plate having a generally rectangular second main electrode portion with a plurality of second lead structures extending therefrom;

(c) said electrode plates being situated in a plane substantially parallel to a plane of said circuit board;

(d) respective ones of said first lead structures being located adjacent respective ones of said second lead structures in an interdigitated arrangement and extending to respective ones of said electrical terminals; and

(e) a ceramic material located between each opposing set of said first and second electrode plates to provide a predetermined dielectric constant.

11. An electrical circuit arrangement as set forth in claim 10, wherein said electrical terminals are located on at least one lateral side of said capacitor body.

12. An electrical circuit arrangement as set forth in claim 11, wherein said electrical terminals are located on both lateral sides of said capacitor body.

13. An electrical circuit arrangement as set forth in claim 11, wherein said capacitor body further includes first and second testing terminals at each end thereof electrically unconnected to said electrical current paths of said circuit board, said first testing terminal being electrically connected to said first electrode plate and said second testing terminal being electrically connected to said second electrode plate.

14. An electrical circuit arrangement as set forth in claim 10, wherein said capacitor body has an aspect ratio of no more than approximately 1:

1.

15. An electrical circuit arrangement as set forth in claim 14, wherein said capacitor body has an aspect ratio of no more than approximately 0.5:

1.

16. An electrical circuit arrangement as set forth in claim 10, wherein said electrical terminals are electrically connected to said predetermined ones of said current paths utilizing eutectic solder.

17. An electrical circuit arrangement as set forth in claim 10, wherein each lateral side of said first main electrode portion has an equal number of said first lead structures and each lateral side of said second main electrode portion has an equal number of said second lead structures.

18. An electrical circuit arrangement as set forth in claim 17, wherein:

said first lead structures extending from a first lateral side of said first main electrode portion are offset by one terminal position in relation to said first lead structures extending from a second lateral side of said first main electrode portion; and

said second lead structures extending from a first lateral side of said second main electrode portion are offset by one terminal position in relation to said second lead structures extending from a second lateral side of said second main electrode portion.

19. An electrical circuit arrangement as set forth in claim 18, wherein each lateral side of said first and second main electrode portions has a total of two lead structures extending therefrom.

20. An electrical circuit arrangement as set forth in claim 10, comprising a plurality of said first electrode plates respectively interleaved with a plurality of said second electrode plates.

21. A multilayer ceramic capacitor comprising:

a low-aspect capacitor body having a unitary structure characteristic of a plurality of stacked, pressed and sintered ceramic-electrode layers;

said capacitor body including a plurality of first polarity electrical terminals and a plurality of second polarity electrical terminals located on the outer surface thereof, said plurality of electrical terminals being formed by a thick-film terminal material;

each ceramic-electrode layer including an electrode plate having a main electrode portion with a plurality of lead structures extending therefrom, said electrode plates being interleaved such that 15 respective lead structures of first alternating electrode plates are electrically connected to respective first polarity terminals and respective lead structures of second alternating electrode plates are electrically connected to respective second polarity terminals; and

wherein said capacitor is constructed and arranged to exhibit an inductance of less than approximately 100 picohenries.

22. A multilayer ceramic capacitor as set forth in claim 21, wherein said low-aspect capacitor body has an aspect ratio of no more than 0.5:

1.

23. A multilayer ceramic capacitor as set forth in claim 21, wherein said respective lead structures of said first alternating electrode plates are located adjacent said respective lead structures of said second alternating electrode plates in an interdigitated arrangement.

24. A multilayer ceramic capacitor as set forth in claim 23, wherein:

said capacitor body has a generally rectangular configuration defining lateral sides of greater dimension and end sides of lesser dimension; and

respective ones of said lateral sides each have an equal number of said first polarity terminals and said second polarity terminals.

25. A multilayer ceramic capacitor as set forth in claim 23, wherein each of said lateral sides has two of said first polarity terminals and two of said second polarity terminals.

26. A multilayer ceramic capacitor as set forth in claim 25, wherein a centerline spacing between a respective first polarity terminal and an adjacent second polarity terminal is no greater than approximately 0.03 inches.

27. A multilayer ceramic capacitor as set forth in claim 25, wherein:

respective said first polarity terminals on a first lateral side of said capacitor body are offset by one terminal position in relation to respective first polarity terminals located on a second lateral side of said capacitor body; and

respective said second polarity terminals on said first lateral side are offset by one terminal position in relation to respective said second polarity terminals located on said second lateral side.

28. A capacitor array having a plurality of capacitor devices in a surface mount compatible package, said array comprising:

a capacitor body having a unitary structure characteristic of a plurality of stacked, pressed and sintered ceramic-electrode layers, said ceramic electrode layers comprising a plurality of first ceramic-electrode layers and a plurality of second ceramic-electrode layers;

said capacitor body including a plurality of first polarity electrical terminals and a plurality of second polarity electrical terminals located on the outer surface thereof;

said first ceramic-electrode layers including an electrode plate having a first main electrode portion with a plurality of first lead structures extending therefrom;

said second ceramic-electrode layers including at least four coplanar second electrode plates situated in opposed and spaced apart relation to said first electrode plate, said second electrode plates each having a second main electrode portion with at least one second lead structure extending therefrom;

respective ones of said first lead structures being located adjacent respective ones of said second lead structures in an interdigitated arrangement and extending to respective ones of said electrical terminals;

wherein said capacitor array has a number of capacitor devices equal to a number of said second electrode plates.

29. A capacitor array as set forth in claim 28, wherein each of said first main electrode portions has at least two of said first lead structures extending therefrom.

30. A capacitor array as set forth in claim 29, wherein each of said first main electrode portions has at least four of said first lead structures extending therefrom.