Half-message based multiplex communication interface circuit which uses a main microcontroller to detect a match in addresses and generate a qualified signal

• US 5,881,063 A
• Filed: 04/08/1996
• Issued: 03/09/1999
• Est. Priority Date: 04/08/1996
• Status: Expired due to Fees

• Current Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Original Assignee: Ford Motor Company
• Inventors: Bement, Bradley Earl, Crawford, Robert Dennis
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Vincent, David R
• Application Number:
  US08/629,252
• Time in Patent Office: 1,065 Days
• Field of Search: 370/212, 370/389, 370/419, 370/522
• US Class Current: 370/389
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: Y04S 40/20 Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Abstract

A method and circuit for receiving frame messages connected to one or more nodes, each controlled by a microcontroller, along a common transmission line of a multiplex communication system. The method includes the steps of: (a) receiving the type and target bytes, and responsive thereto generating a first interrupt signal to the microcontroller at the node; (b) commanding the microcontroller, responsive to receiving the first interrupt signal, for qualifying the frame message by retrieving and matching one or more of the type and target bytes with corresponding bytes stored in programmable memory within the microcontroller, and responsive thereto generating a qualified signal; and (c) receiving data bytes from the frame message only responsive to receiving the qualified signal from the microcontroller.

Claims

1. A method for receiving frame messages communicated to one or more nodes, each controlled by a microcontroller, along a common transmission line of a multiplex communications system, comprising the steps of:

(a) receiving type and target bytes and responsive thereto generating a first interrupt signal to the microcontroller,

(b) commanding the microcontroller, responsive to receiving the first interrupt signal, for qualifying the frame message by retrieving and matching one or more of the type and target bytes with corresponding bytes stored therein, and responsive thereto generating a qualified signal,

(c) receiving and storing data bytes from the frame message into temporary memory for subsequent processing only responsive to receiving the qualified signal from the microcontroller,

(d) calculating a CRC value from, and generating a corresponding CRC signal representative of, the integrity of the data bytes received from the frame message; and

(e) generating a second interrupt signal, responsive to receiving a valid CRC signal, for commanding the microcontroller to fetch the data bytes.

2. The method as described in claim 1 wherein step (b) further comprises the substep:

(b1) generating the qualified signal only responsive to one or more of the type and target bytes matching corresponding bytes stored in a programmable memory within the microcontroller, whereby the qualified signal is representative of the frame message being directed to the node for processing.

3. The method as described in claim 1 wherein step (d) further comprises the substeps of:

(d1) generating an acknowledge signal, responsive to receiving a valid CRC signal and an End of Data bit, for transmission to the node transmitting the message frame.

4. The method as described in claim 1 wherein step (a) further comprises the substep of:

(a1) confirming that the frame message is a PWM digital signal complying with an automobile industrial standard for data communications network interfaces.

5. An interface device, interposed between a transmission line of a multiplex communications system and a microcontroller, for receiving frame messages communicated to one or more nodes, said interface device comprising in combination:

a qualification memory coupled to the transmission line for receiving type and target bytes of the frame message, and responsive thereto generating a first interrupt signal;

an interface controller, coupled to said qualification memory and the microcontroller, for commanding, responsive to receiving said first interrupt signal, the microcontroller to retrieve and match one or more of the type and target bytes with corresponding bytes stored in the microcontroller and responsive thereto generating a qualified signal; and

a receive memory for receiving and storing, responsive to receiving said qualified signal, data bytes of the frame message, whereby the data bytes of the frame message are received in said receive memory but stored only responsive to the microcontroller generating said qualified signal.

6. The interface device as described in claim 5, wherein the microcontroller is of the type that includes programmable memory for storing therein selected type and target bytes representative of the function(s) and address of the node, and qualification means for comparing the type and target bytes from the frame message therewith and generating said qualified signal responsive only to at least one match therebetween.

7. The interface device as described in claim 5 further comprising error detecting means, coupled to the transmission line of the multiplex communication system, for receiving the frame message and generating a CRC signal representative of the integrity of the data bytes therein.

8. The interface device as described in claim 7 wherein said interface controller further comprises acknowledge means for generating an in-frame acknowledge signal responsive to receiving both a valid one of said CRC signals and an End of Data bit, whereby the node originating the message frame will receive acknowledgment that the frame message has been received by the intended node(s).

9. The interface device as described in claim 8 wherein said acknowledge means further comprises:

means for commanding the microcontroller, responsive to receiving said valid one of said CRC signals, to fetch the data bytes from said receive memory; and

means for generating said acknowledge signal responsive to receiving said valid one of said CRC signals and an End of Data bit from the frame message.

10. A method for receiving frame messages communicated to one or more nodes, each controlled by a microcontroller, along a common transmission line of a multiplex communications system, comprising the steps of:

(a) receiving type and target bytes in a qualification memory and responsive thereto generating a first interrupt signal,

(b) commanding the microcontroller, responsive to receiving the first interrupt signal, to qualify the frame message by retrieving, from the qualification memory, and matching one or more of the type and target bytes with corresponding bytes stored therein, and responsive thereto generating a qualified signal; and

(c) receiving and storing data bytes in receive memory only responsive to receiving the qualified signal from the microcontroller, whereby the data bytes from the frame message are stored only after qualification of the type and target bytes.

11. The method as described in claim 10 further comprising the steps of:

(d) calculating a CRC value from, and generating a corresponding CRC signal representative of, the integrity of the bytes in the frame message; and

(e) generating a second interrupt signal responsive to receiving a valid CRC signal, for commanding the microcontroller to fetch the data bytes from the receive memory.

12. The method as described in claim 11 further comprising the step of:

(f) processing the data bytes in the microcontroller responsive to receiving the second interrupt signal.

13. The method as described in claim 11 wherein step (d) further comprises the substeps of:

(d1) generating an in-frame acknowledge signal, responsive to receiving a valid CRC signal and an End of Data byte, for transmission to the node transmitting the message frame.

14. The method as described in claim 10 wherein step (a) further comprises the substeps of:

(a1) confirming that the frame message is a PWM digital signal complying with a Society of Automotive Engineers standard for data communications network interfaces.

15. An interface device, interposed between a microcontroller and a transmission line, for receiving frame messages communicated to one or more nodes along the transmission line in a multiplex communications system, comprising in combination:

a qualification memory coupled to the transmission line for receiving type and target bytes of the frame message, and responsive thereto generating a first interrupt signal;

an interface controller, coupled to said qualification memory and the microcontroller, for commanding, responsive to receiving said first interrupt signal, the microcontroller to retrieve and match one or more of the type and target bytes with corresponding bytes stored in the microcontroller and responsive thereto generating, before reception of the data bytes in the message frame is complete, a qualified signal; and

a receive memory, coupled to said interface controller and the transmission line, for receiving and then storing, only responsive to receiving said qualified signal, data bytes of the frame message, whereby the microcontroller qualifies, before reception of the data bytes is complete, the frame message using only the type and target bytes.

16. The interface device as described in claim 15, wherein the microcontroller has stored therein selected type and target bytes representative of the functions and address of the node, and includes means for comparing the type and target bytes from the frame message therewith and for generating said qualified signal responsive to a match defined by the microcontroller.

17. The interface device as described in claim 15 further comprising error detecting means, coupled to the transmission line, for receiving the frame message and generating a CRC signal representative of the integrity of the bytes therein.

18. The interface device as described in claim 17 further comprising acknowledge means for generating an in-frame acknowledge signal responsive to receiving said qualified signal, a valid one of said CRC signals and an End of Data byte, whereby the node originating the message frame will receive acknowledgment that the frame message has been received and qualified by the intended node(s).

19. The interface device as described in claim 18 wherein said acknowledge means comprises:

means for commanding the microcontroller, responsive to receiving said valid one of said valid CRC signals, to store and fetch the data bytes from said temporary memory; and

means for generating said acknowledge signal responsive to receiving said valid one of said CRC signals and an End of Data byte from the frame message.

20. The interface device as described in claim 15 wherein the microcontroller generates said qualified signal prior to said receive memory receiving an End of Data byte in the frame message.

21. A method for receiving frame messages communicated to one or more nodes, each controlled by a microcontroller, along a common transmission line of a multiplex communications system, comprising the steps of:

(a) receiving type and target bytes in a qualification memory and responsive thereto immediately generating a first interrupt signal,

(b) commanding the microcontroller, responsive to receiving the first interrupt signal, to qualify the frame message by retrieving, from the qualification memory, and matching one or more of the type and target bytes with corresponding bytes stored in the microcontroller, and responsive thereto generating a qualified signal; and

(c) receiving and storing data bytes in receive memory only responsive to receiving the qualified signal from the microcontroller, whereby the data bytes from the frame message are stored only after qualification of the frame message through the type and target bytes.

22. The method as described in claim 21 further comprising the steps of:

(d) calculating a CRC value from, and generating a corresponding CRC signal representative of, the integrity of the bytes in the frame message; and

(e) generating a second interrupt signal responsive to receiving a valid CRC signal, for commanding the microcontroller to fetch the data bytes from the receive memory.

23. The method as described in claim 21 further comprising the step of:

(f) receiving and processing the data bytes in the microcontroller responsive to receiving the second interrupt signal.

24. The method as described in claim 23 wherein step (a) further comprises the substep of:

(a1) receiving only the type and target bytes before generating the first interrupt signal.

25. The method as described in claim 21 wherein step (c) further comprises the substep of:

(c1) temporarily receiving data bytes in a temporary memory pending receipt of the qualified signal form the microcontroller.

26. An interface device, interposed between a microcontroller and a transmission line, for receiving frame messages communicated to one or more nodes along the transmission line in a multiplex communications system, comprising in combination:

a qualification memory coupled to the transmission line for receiving only the type and target bytes of the frame message, and the promptly generating a first interrupt signal responsive thereto;

an interface controller, coupled to said qualification memory and the microcontroller, for commanding, responsive to receiving said first interrupt signal, the microcontroller to retrieve and match one or more of the type and target bytes with corresponding bytes stored in the microcontroller and then promptly generating a qualified signal responsive thereto; and

a receive memory, coupled to the transmission line and the microcontroller, for receiving and storing, responsive to receiving said qualified signal, data bytes from the frame message, whereby the microcontroller qualifies the frame message after receiving only the type and target bytes.

27. The interface device as described in claim 26, wherein the microcontroller has stored therein selected type and target bytes representative of the functions and address of the intended nodes, and includes means for comparing the type and target bytes from the frame message therewith and generating said qualified signal responsive to a match defined therebetween.

28. The interface device as described in claim 26 wherein said receive memory further includes temporary memory for receiving and temporarily storing therein data bytes from the frame message pending receipt of said qualified signal.

29. The interface device as described in claim 26 wherein the microcontroller generates said qualified signal before completion of the reception of the data bytes.

30. The interface device as described in claim 29 further comprising error detecting means, coupled to the transmission line, for receiving the frame message and generating a CRC signal representative of the integrity of the bytes therein.

31. The interface device as described in claim 30 further comprising acknowledge means for generating an in-frame acknowledge signal responsive to receiving said qualified signal, a valid one of said CRC signals and an End of Data byte, whereby the node originating the message frame will receive acknowledgment that the frame message has been received and qualified by the intended node(s).

32. The interface device as described in claim 31 wherein said acknowledge means comprises:

means for commanding the microcontroller, responsive to receiving said valid one of said valid CRC signals, to store and fetch the data bytes from said receive memory; and

means for generating said acknowledge signal responsive to receiving said valid one of said CRC signals and an End of Data byte from the frame message.