Efficient demodulation scheme for DSSS communication

• US 5,881,098 A
• Filed: 02/21/1996
• Issued: 03/09/1999
• Est. Priority Date: 02/21/1996
• Status: Expired due to Term

• Current Assignee: Transpacific IP I Limited (Transpacific IP Group Limited)
• Original Assignee: Industrial Technology Research Institute
• Inventors: Tzou, Ching-Kae
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/604,473
• Time in Patent Office: 1,112 Days
• Field of Search: 375/200, 375/206, 375/207, 375/208, 375/343
• US Class Current: 375/152
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A DSSS receiver for processing a complex spread-spectrum signal which contains source information, the receiver including a despreading circuit which despreads a first complex signal that is derived from the spread-spectrum signal to produce a second complex signal; a differential demodulator which differentially demodulates the second complex signal to generate a third complex signal; and a sum and dump circuit which during each of successive symbol periods of the third complex signal sums multiple samples of the third complex signal to produce a fourth complex signal, wherein decision processing is performed in the fourth complex signal to extract the source information.

Claims

1. A DSSS receiver for processing a complex spread-spectrum signal which contains source information, said receiver comprising:

a despreading circuit which despreads a first complex signal that is derived from the spread-spectrum signal to produce a second complex signal;

a differential demodulator which is directly coupled to the despreading circuit and which differentially demodulates the second complex signal to generate a third complex signal; and

a sum and dump circuit which during each of successive symbol periods of the third complex signal sums multiple samples of the third complex signal to produce a fourth complex signal, wherein decision processing is performed in the fourth complex signal to extract the source information;

wherein the differential demodulator includes;

a delay circuit which delays the second complex signal by a symbol period to generate a delayed signal;

a module which generates a complex conjugate of the delayed signal; and

a multiplier which multiplies the second complex signal by the complex conjugate of the delayed signal to produce the third complex signal.

2. The receiver of claim 1 further comprising a mixer which multiplies the complex spread-spectrum signal by quadrature and in-phase components of a complex reference signal to generate said first complex signal.

3. The receiver of claim 1 wherein the despreading circuit is a match filter.

4. The receiver of claim 1 wherein the despreading circuit is a linear correlator.

5. The receiver of claim 1 further comprising a power detector which controls operation of the sum and dump circuit based on the spread-spectrum signal.

6. The receiver of claim 1 further comprising a power detector which controls operation of the sum and dump circuit based on the second complex signal.

7. The receiver of claim 1 further comprising a QPSK decision module which extracts the source information from the fourth complex signal.

8. The receiver of claim 7 further comprising a power detector which controls operation of the differential demodulator based on the spread-spectrum signal.

9. The receiver of claim 7 further comprising a power detector which controls operation of the differential demodulator based on the second complex signal.

10. A DSSS receiver for processing a complex spread-spectrum signal which contains source information, said receiver comprising:

a despreading circuit which despreads a first complex signal that is derived from the spread-spectrum signal to produce a second complex signal;

a differential demodulator which is directly coupled to the despreading circuit and which differentially demodulates the second complex signal to generate a third complex signal; and

a circuit which is directly coupled to the differential demodulator and which during each of successive symbol periods performs quantization on the third complex signal to produce a fourth complex signal, wherein decision processing is performed in the fourth complex signal to extract the source information.

11. The receiver of claim 10 wherein the quantization circuit performs a hard decision quantization.

12. The receiver of claim 10 wherein the quantization circuit performs a soft decision quantization.

13. A DSSS receiver of claim 10 wherein the differential demodulator includes:

a delay circuit which delays the second complex signal by a symbol period to generate a delayed signal;

a module which generates a complex conjugate of the delayed signal; and

a multiplier which multiplies the second complex signal by the complex conjugate of the delayed signal to produce the third complex signal.