Signal processing circuit to implement a Viterbi algorithm
First Claim
1. A signal processing circuit comprising a processor, a data memory to store data received and data processed by the signal processing circuit, a program memory to store a plurality of instructions of a processing program, wherein a portion of said plurality of instructions implement a Viterbi algorithm, wherein said circuit comprises a coprocessor linked with the program memory to carry out a processing operation of accumulation, comparison and selection corresponding to the Viterbi algorithm, wherein the coprocessor comprisesadder/subtractor type adders to limit iterative computations undertaken by the coprocessor.
1 Assignment
0 Petitions
Accused Products
Abstract
To carry out the processing operations relating to the implementation of a Viterbi algorithm, an integrated circuit comprising a processor and a coprocessor is made. The coprocessor is constructed so as to carry out operations of accumulation, comparison and selection in order to limit or reduce the work of a processor that would have to carry out these operations. By judiciously choosing the structure of the coprocessor, it is possible to make this co-processor sufficiently programmable so that it is suited to various situations of implementation of the Viterbi algorithm.
120 Citations
15 Claims
-
1. A signal processing circuit comprising a processor, a data memory to store data received and data processed by the signal processing circuit, a program memory to store a plurality of instructions of a processing program, wherein a portion of said plurality of instructions implement a Viterbi algorithm, wherein said circuit comprises a coprocessor linked with the program memory to carry out a processing operation of accumulation, comparison and selection corresponding to the Viterbi algorithm, wherein the coprocessor comprises
adder/subtractor type adders to limit iterative computations undertaken by the coprocessor.
-
3. A signal processing circuit comprising a processor, a data memory to store data received and data processed by the signal processing circuit, a program memory to store a plurality of instructions of a processing program, wherein a portion of said plurality of instructions implement a Viterbi algorithm, wherein said circuit comprises a coprocessor linked with the program memory to carry out a processing operation of accumulation, comparison and selection corresponding to the Viterbi algorithm, wherein the coprocessor comprises
a set of registers whose inputs and outputs are connected to multiplexers to make the coprocessor carry out several simultaneous processing operations at each memory access operation.
-
6. A signal processing circuit comprising a processor, a data memory to store data received and data processed by the signal processing circuit, a program memory to store a plurality of instructions of a processing program, wherein a portion of said plurality of instructions implement a Viterbi algorithm, wherein said circuit comprises a coprocessor linked with the program memory to carry out a processing operation of accumulation, comparison and selection corresponding to the Viterbi algorithm, wherein the coprocessor comprises
two buses so that the coprocessor can alternately be linked, in reading mode and then in writing mode, with two memories and wherein the processor has a circuit to alternate the connections of the coprocessor with each of the buses.
-
9. A method for decoding a received signal implementing a Viterbi algorithm, the method comprising the following steps:
-
a first adding step for adding a first old path metric to a first branch metric to produce a first new path metric; a second adding step for adding a second old path metric to a second branch metric to produce a second new path metric, wherein the first adding step and the second adding step are performed simultaneously; a first comparing step for comparing the first new path metric and the second new path metric to determine a first minimum path metric; a selecting step for selecting one of the first and second new path metrics as the first minimum path metric wherein the first minimum path metric is determined by a comparator, the comparator producing a control signal to control a multiplexer, and wherein the first minimum path metric is selected by the multiplexer; and determining a survivor value based on the control signal of the multiplexer wherein the control signal is stored as the survivor value. - View Dependent Claims (10, 11, 12)
-
-
13. A signal processing system for implementing a Viterbi algorithm, the system comprising:
-
processing means; data memory to store data received and data processed by the signal processing system; program memory to store a plurality of instructions of a processing program, wherein a portion of said plurality of instructions implement a Viterbi algorithm, and coprocessing means operable with program memory for performing a processing operation of accumulations, comparison and selection corresponding to the Viterbi algorithm, wherein coprocessing means includes; means for performing two simultaneous additions; means for comparing the two simultaneous additions; and means for selecting one of the two simultaneous additions. - View Dependent Claims (14, 15)
-
Specification