Driver level diagnostics

• US 5,881,221 A
• Filed: 12/31/1996
• Issued: 03/09/1999
• Est. Priority Date: 12/31/1996
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Fontenot, Paul, Hoang, Thanh V.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Elisca, Pierre E.
• Application Number:
  US08/777,663
• Time in Patent Office: 798 Days
• Field of Search: 395/183.01, 395/183.18, 395/182.22, 371/25.1, 371/40.1, 371/21.1, 371/22.33
• US Class Current: 714/42
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns

Abstract

An apparatus and method are disclosed for testing memory and display adapter components of a multi-tasking computer system. The apparatus obtains a memory block and sends a request to a memory virtual device driver (VxD) to reserve, commit and lock the memory block to a physical memory. In requesting the memory block, the apparatus computes the number of virtual memory pages spanned by the request, reserves the pages of virtual memory, commits the virtual memory to a physical memory, and locks the virtual memory to the physical memory. The apparatus then obtains a physical address for the physical memory and returns the physical address for testing. Next, the apparatus tests the memory block using a number of memory test procedures. After the testing completes, the apparatus decommits and unlocks the physical memory before it traverses to the next entry of the chain. This process is repeated until all entries in the virtual memory chain have been tested. The apparatus also tests the video memory by generating a pattern, writing the pattern to the video memory; reading the content of the video memory and comparing the pattern against the content of the video memory. In the event that the content of the video memory differs from the pattern, the apparatus indicates a defective video display adapter and otherwise indicates a good video display adapter.

Claims

1. A method for testing components of a multi-tasking computer system with a virtual memory chain, said method comprising:

(a) obtaining a memory block having a memory base address and a memory base length for a current entry in the virtual memory chain;

(b) sending a request to a memory virtual device driver (VxD) to reserve, commit and lock said memory block to a physical memory;

(c) testing said memory block located at said memory base address and said memory length;

(d) decommit and unlock said physical memory after step (c);

(e) traversing to a next entry in said chain; and

(f) repeating steps (a)-(e) until all entries in said virtual memory chain have been tested.

2. The method of claim 1, wherein step (a) further comprises the step of checking for a valid range for said memory block.

3. The method of claim 1, wherein step (c) further comprises the step of selecting a memory read/write/check test, a memory noise test, a random pattern memory test, a random address memory test, or an address memory test.

4. The method of claim 3, wherein said read/write/check test further comprises the steps of:

writing a known pattern into said memory block;

waiting for a predetermined period;

comparing the result of said writing step with a predetermined bit pattern; and

if said comparing step indicates a difference, converting said base address into a physical address and indicating a memory error.

5. The method of claim 4, wherein said known pattern include patterns selected from a noise test, a random pattern test, a random address test, an address test, a marching test, and a walking zeros and ones test.

6. The method of claim 1, wherein step (b) further comprises the steps of

generating a number of virtual memory pages spanned by said request;

reserving said pages of virtual memory;

committing said virtual memory to a physical memory;

locking said virtual memory to said physical memory;

obtaining a physical address of said physical memory; and

returning said physical address for testing.

7. The method of claim 1, wherein step (d) further comprises the steps of:

unlocking said virtual memory from said physical memory; and

freeing said physical memory.

8. The method of claim 1, wherein said computer system has a video display system with a video memory, said method further comprising the step of testing for display modes of said video display system.

9. The method of claim 1, wherein said computer system has a video display system with a video memory and graphics accelerator circuitry, said method further comprising the step of testing one or more accelerator functions.

10. The method of claim 1, wherein said computer system has a video display system with a video memory, said method further comprising the step of interacting with a user.

11. The method of claim 10, wherein said interacting step further comprises the steps of:

generating a random number;

obtaining data from said user;

comparing said data with said random number; and

if said data differs from said random number generator, indicating failure, and otherwise indicating success.

12. The method of claim 1, wherein said computer system has a video display system with a video memory, said method further comprising the steps of:

generating a cyclic redundancy code for said video memory;

comparing said cyclic redundancy code with a predetermined value; and

if said cyclic redundancy code differs from said predetermined value, indicating failure, and otherwise indicating success.

13. The method of claim 12, wherein said cyclic redundancy code is determined using a Direct Draw Driver.

14. The method of claim 12, wherein said cyclic redundancy code is determined using the steps of:

(a) accessing a video memory location;

(b) adding the content of said memory location to said cyclic redundancy code; and

(c) repeating steps (a) and (b) until all video memory locations have been accessed.

15. The method of claim 1, wherein said computer system has a video display system with a video memory, said method further comprising the steps of:

generating a random pattern;

writing said random pattern to said video memory;

reading the content of said video memory;

comparing said random pattern to the content of said video memory; and

if the content of said video memory differs from said random pattern, indicating an error and otherwise indicating a success.

16. The method of claim 1, wherein said computer system has a video display system with a video memory, said method further comprising the steps of:

retrieving a predetermined pattern;

writing said predetermined pattern to said video memory;

reading the content of said video memory;

comparing said predetermined pattern to the content of said video memory; and

if the content of said video memory differs from said predetermined pattern, indicating an error and otherwise indicating a success.

17. The method of claim 1, wherein said computer system has a video display system with a power management mode, said method further comprising the steps of:

setting said power management state;

delaying for a predetermined period;

checking for a blank video display; and

if said video display is not blank, indicating failure and otherwise indicating success.

18. The method of claim 17, wherein said setting step sets said power management state through a VESA BIOS call.

19. The method of claim 1, wherein said computer system has a video display system with a video memory, said method further comprising the step of selecting a mode test, an accelerator test, a video memory test, or a power management test.

20. A method for testing components of a multi-tasking computer system with a virtual memory chain and a video display system with a video memory, said method comprising:

(a) obtaining a memory block having a memory base address and a memory base length for the current entry in the virtual memory chain;

(b) sending a request to a memory virtual device driver (VxD) to reserve, commit and lock said memory block to a physical memory, further including the steps of;

generating a number of virtual memory pages spanned by said request;

reserving said pages of virtual memory;

committing said virtual memory to a physical memory;

locking said virtual memory to said physical memory;

obtaining a physical address of said physical memory; and

returning said physical address for testing;

(c) testing said memory block located at said memory base address and said memory length;

(d) decommit and unlock said physical memory after step (c);

(e) traversing to the next entry in said chain;

(f) repeating steps (a)-(e) until all entries in said virtual memory chain have been tested;

(g) if step (c) detected a memory failure, indicating a memory failure and otherwise indicating a good memory; and

(h) testing said video memory, further comprising the steps of;

generating a pattern;

writing said pattern to said video memory;

reading the content of said video memory;

comparing said pattern to the content of said video memory; and

if the content of said video memory differs from said pattern, indicating a defective video display system and otherwise indicating a good video display system.

21. A program storage device having a computer readable code embedded therein for testing components of a multi-tasking computer system with a virtual memory chain, said program storage device comprising:

a first code for obtaining a memory block having a memory base address and a memory base length for a current entry in the virtual memory chain;

a second code for sending a request to a memory virtual device driver (VxD) to reserve, commit and lock said memory block to a physical memory;

a third code for testing said memory block located at said memory base address and said memory length;

a fourth code for decommit and unlock said physical memory; and

a fifth code for traversing to a next entry in said chain.

22. The program storage device of claim 21, wherein said first code further comprises a code for checking for a valid range for said memory block.

23. The program storage device of claim 21, wherein said third code further comprises a code for selecting a memory read/write/check test, a memory noise test, a random pattern memory test, a random address memory test, or an address memory test.

24. The program storage device of claim 23, wherein said read/write/check test further comprises:

a seventh code for writing a known pattern into said memory block;

a eighth code for waiting for a predetermined period;

a ninth code for comparing the result of said seventh code with a predetermined bit pattern; and

a tenth code for converting said base address into a physical address and indicating a memory error if said comparing code indicates a difference.

25. The program storage device of claim 24, wherein said known pattern include patterns selected from a noise test, a random pattern test, a random address test, an address test, a marching test, and a walking zeros and ones test.

26. The program storage device of claim 21, wherein said second code further comprises:

a page count code for generating a number of virtual memory pages spanned by said request;

a reservation code for reserving said pages of virtual memory;

a commit code for committing said virtual memory to a physical memory;

a lock code for locking said virtual memory to said physical memory; and

an address code for obtaining a physical address of said physical memory.

27. The program storage device of claim 21, wherein said fourth code further comprises:

an unlock code for unlocking said virtual memory from said physical memory; and

an unallocate code for freeing said physical memory.

28. The program storage device of claim 21, wherein said computer system has a video display system with a video memory, said program storage device comprising a code for testing display modes of said video display system.

29. The program storage device of claim 21, wherein said computer system has a video display system with a video memory and graphics accelerator circuitry, said program storage device further comprising a code for testing one or more accelerator functions.

30. The program storage device of claim 21, wherein said computer system has a video display system with a video memory, said program storage device comprising a code for interacting with a user.

31. The program storage device of claim 30, wherein said interacting code further comprises:

a random number code for generating a random number;

a data input code for receiving data from said user;

a comparator code for comparing said data with said random number; and

a display code for indicating failure if said data differs from said random number generator and otherwise indicating success.

32. The program storage device of claim 21, wherein said computer system has a video display system with a video memory, said program storage device further comprising:

a code generator for generating a cyclic redundancy code for said video memory;

a comparator code for comparing said cyclic redundancy code with a predetermined value; and

a display code for indicating failure if said cyclic redundancy code differs from said predetermined value and otherwise indicating success.

33. The program storage device of claim 32, wherein said cyclic redundancy code is determined using a Direct Draw Driver.

34. The program storage device of claim 32, wherein said code generator further comprises:

a code for accessing the content of a video memory location; and

an adder code for adding the content of said video memory location to said cyclic redundancy code.

35. The program storage device of claim 21, wherein said computer system has a video display system with a video memory, said program storage device further comprising:

a code for generating a random pattern;

a code for writing said random pattern to said video memory;

a code for reading the content of said video memory;

a code for comparing said random pattern to the content of said video memory; and

a display code for indicating an error and otherwise indicating a success.

36. The program storage device of claim 21, wherein said computer system has a video display system with a video memory, said program storage device further comprising:

a code for retrieving a predetermined pattern;

a code for writing said predetermined pattern to said video memory;

a code for reading the content of said video memory;

a code for comparing said predetermined pattern to the content of said video memory; and

a code for indicating an error if the content of said video memory differs from said predetermined pattern and otherwise indicating a success.

37. The program storage device of claim 21, wherein said computer system has a video display system with a power management mode, said program storage device further comprising:

a code for setting said power management state;

a code for delaying for a predetermined period;

a code for checking for a blank video display; and

a display code for indicating failure if said video display is not blank and otherwise indicating success.

38. The program storage device of claim 37, wherein said setting code sets said power management state through a VESA BIOS call.

39. The program storage device of claim 21, wherein said computer system has a video display system with a video memory, said program storage device further comprising a code for selecting a mode test, an accelerator test, a video memory test, or a power management test.