Non-instruction base register addressing in a data processing apparatus

• US 5,881,263 A
• Filed: 10/08/1996
• Issued: 03/09/1999
• Est. Priority Date: 09/23/1996
• Status: Expired due to Term

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: York, Richard, Frances, Hedley James, Symes, Dominic, Biles, Stuart
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US08/727,338
• Time in Patent Office: 882 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/393
• US Class Current: 712/217
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

The present invention provides a data processing apparatus comprising: a plurality of registers for storing data items to be processed; a processor for processing instructions to be applied to data items stored in said plurality of registers; and register remapping logic for converting a logical register reference within a preselected set of instructions to a physical register reference identifying the register containing the data item required for processing by the processor.

By this approach, a remapping instruction need only be executed once in order for the remapping to be applied to a desired number of instructions. This is in contrast to prior art techniques, where subsequent to a remapping instruction being executed, the remapping is applied to all subsequent instructions, ie. a desired number of instructions cannot be selected.

The invention is particularly advantageously employed in apparatus arranged to repeat an instruction loop, the instruction loop including said preselected set of instructions. In such cases, loop hardware used to manage the repeat instruction can be arranged to update the register remapping logic each time the instruction loop is repeated, and hence the remapping instruction used to configure the register remapping logic is only executed once prior to the repeat instruction being executed.

Claims

1. A data processing apparatus comprising:

(i) a plurality of registers for storing data items to be processed;

(ii) a processor for processing instructions to be applied to data items stored in said plurality of registers;

(iii) register remapping logic for converting a logical register reference within a preselected set of instructions to a physical register reference identifying the register containing the data item required for processing by said processor;

(iv) a repeat instruction for defining a range of instructions to be repeated, said range of instructions comprising said preselected set of instructions; and

(v) loop hardware for managing the repeat instruction and arranged to periodically update the register remapping logic so as to alter the logical register reference to physical register reference applied by said register remapping logic.

2. A data processing apparatus as claimed in claim 1, wherein the repeat instruction includes one or more remapping parameters used to configure the register remapping logic.

3. A data processing apparatus as claimed in claim 2, wherein the register remapping logic is arranged to perform remapping on a number of said plurality of registers, and a base pointer is used by the register remapping logic as an offset value to be added to the logical register reference, the repeat instruction including a second remapping parameter identifying a value by which the base pointer is incremented at predetermined internals.

4. A data processing apparatus as claimed in claim 3, wherein the repeat instruction includes a third remapping parameter providing a first wrapping value, and if during the incrementing of the base pointer, the base pointer becomes equal to or exceeds the first wrapping value, the incrementing of the base pointer wraps round to a new offset value.

5. A data processing apparatus as claimed in claim 3, wherein the repeat instruction includes a fourth remapping parameter providing a second wrapping value, and if the register reference formed by the addition of the base pointer and the logical register reference equals or exceeds the second wrapping value, then that register reference is wrapped round to a new register reference.

6. A data processing apparatus as claimed in claim 2, wherein a remapping instruction is arranged to be performed prior to execution of the repeat instruction to configure the register remapping logic using said one or more remapping parameters, said remapping instruction not being included within said range of instructions defined by the repeat instruction.

7. A data processing apparatus as claimed in claim 2, further comprising a storage means for storing at least one set of predefined remapping parameters, each set defining a remapping configuration for said register remapping logic, wherein if said one or more remapping parameters included in said repeat instruction correspond to one of said sets of predefined remapping parameters, then the corresponding remapping configuration for the register remapping logic is used without requiring a remapping instruction to be executed.

8. A data processing apparatus as claimed in claim 2, wherein a first remapping parameter identifies a number of said plurality of registers to be subject to remapping by the register remapping logic.

9. A data processing apparatus as claimed in claim 1, wherein said plurality of registers contains banks of registers, the register remapping logic being arranged to perform remapping on a number of registers within a particular bank.

10. A data processing apparatus as claimed in claim 9, wherein the register remapping logic is arranged to perform an independent remapping for each bank of registers.

11. A data processing apparatus as claimed in claim 1, wherein the register remapping logic is configurable by a remapping instruction arranged to be processed prior to said preselected set of instructions.

12. A data processing apparatus as claimed in claim 1, wherein the loop hardware is arranged to update the register remapping logic each time the range of instructions are repeated.

13. A data processing apparatus as claimed in claim 1, wherein an instruction includes a plurality of operands, each operand comprising a logical register reference, and the register remapping logic is arranged to perform an independent remapping for each operand.

14. A data processing apparatus as claimed in claim 1, wherein the apparatus is a digital signal processing apparatus.

15. A method of operating a data processing apparatus, comprising:

(a) storing within a plurality of registers data items to be processed;

(b) retrieving from the plurality of registers one or more data items required for processing an instruction;

(c) processing the instruction using said one or more data items retrieved;

including, if the instruction is one of a preselected set of instructions, employing register remapping logic to convert a logical register reference within said instruction to a physical register reference identifying the register containing the data item required for processing said instruction;

(d) defining a range of instructions to be repeated, said range of instructions comprising said preselected set of instructions; and

(e) employing loop hardware to manage the repeat instruction and to periodically update said register remapping logic so as to alter the logical register reference to physical register reference conversion applied by the register remapping logic.

16. A method as claimed in claim 15, wherein the step of defining a range of instructions to be repeated includes the step of defining one or more remapping parameters to be used to configure the register remapping logic.

17. A method as claimed in claim 16, wherein a remapping instruction is arranged to be performed, prior to execution of the range of instructions to be repeated, to configure the register remapping logic using said one or more remapping parameters.

18. A method as claimed in claim 16, further comprising the steps of:

storing at least one set of predefined remapping parameters, each set defining a remapping configuration for said register remapping logic; and

if said one or more remapping parameters correspond to one of said sets of predefined remapping parameters, then using the corresponding remapping configuration for the register remapping logic without requiring a remapping instruction to be executed.

19. A method as claimed in claim 15, wherein said plurality of registers contains banks of registers, the method comprising the step of performing remapping on a number of registers within a particular bank.

20. A method as claimed in claim 19, further comprising the step of performing an independent remapping for each bank of registers.

21. A method as claimed in claim 15, wherein the loop hardware is arranged to update the register remapping logic each time the range of instructions are repeated.

22. A method as claimed in claims 15, wherein an instruction includes a plurality of operands, each operand comprising a logical register reference, and the method further comprises the step of performing an independent remapping for each operand.

23. A data processing apparatus comprising:

(i) a plurality of registers for storing data items to be processed;

(ii) a processor for processing instructions to be applied to data items stored in said plurality of registers; and

(iii) hardware register remapping logic for converting a logical register reference within a preselected set of instructions to a physical register reference identifying the register containing the data item required for processing by said processor independent of said processing instructions.

24. A method of operating a data processing apparatus, comprising:

(a) storing within a plurality of registers data items to be processed;

(b) retrieving from the plurality of registers one or more data items required for processing an instruction;

(c) processing the instruction using said one or more data items retrieved;

said retrieving step (b) comprising, for a preselected set of instructions, the additional hardware implemented step of converting a logical register reference within said preselected set of instructions to a physical register reference identifying the register containing the data item required for said processing step (c), independent of said processing instructions.