Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors on write to program counter of one processor
First Claim
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1. A synchronization system comprising:
- a synchronization bus having a plurality of bus lines;
a plurality of processors, equal in number to the number of bus lines in said synchronization bus, each processor fetching and executing instructions independently of other processors, each processor includinga program counter register storing an address of a next instruction for fetching said next instruction,a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor,an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction, said okay to synchronize circuit inhibiting generation of said okay to synchronize signal during an interval from the storing of a changed address in said program counter other than a next sequential address until execution of an instruction at said changed address,a synchronization logic unit connected to said synchronization bus, said program counter register and said synchronization register for inhibiting the fetching of said next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus, thereafter permitting the fetching of said next instruction by said program counter register, andan execution unit for executing fetched instructions, whereby each processor is synchronized to said other of said processors indicated in said synchronization register on an instruction by instruction basis.
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Abstract
A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.
98 Citations
27 Claims
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1. A synchronization system comprising:
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a synchronization bus having a plurality of bus lines; a plurality of processors, equal in number to the number of bus lines in said synchronization bus, each processor fetching and executing instructions independently of other processors, each processor including a program counter register storing an address of a next instruction for fetching said next instruction, a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor, an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction, said okay to synchronize circuit inhibiting generation of said okay to synchronize signal during an interval from the storing of a changed address in said program counter other than a next sequential address until execution of an instruction at said changed address, a synchronization logic unit connected to said synchronization bus, said program counter register and said synchronization register for inhibiting the fetching of said next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus, thereafter permitting the fetching of said next instruction by said program counter register, and an execution unit for executing fetched instructions, whereby each processor is synchronized to said other of said processors indicated in said synchronization register on an instruction by instruction basis. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. The method of operating a computer system having a plurality of processors in synchronism, each of the processors independently fetching and executing instructions, said method comprising the steps of:
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storing in a program counter an address of a next sequential instruction to be executed by said processor; generating at each processor a ready signal when said processor is ready to fetch an instruction; storing at each processor an indication of other processor or processors to which said processor is to be synchronized; inhibiting fetching a next instruction at each processor until said processor receives said ready signal from all other processor or processors to which said processor is to be synchronized according to said stored indication and thereafter fetching said instruction at each processor; inhibiting fetching an instruction at each processor during an interval from the storing of a changed address in a program counter other than a next sequential address until execution of an instruction at said changed address at any one processor from all other processor or processors to which said processor is to be synchronized according to said stored indication; and executing fetched instructions at each processor, whereby each processor is synchronized with said other processor or processors according to said stored indication on an instruction by instruction basis. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification