Method and apparatus for automatically loading configuration data on reset into a host adapter integrated circuit

• US 5,881,281 A
• Filed: 10/21/1997
• Issued: 03/09/1999
• Est. Priority Date: 09/07/1994
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Gates, Stillman F., Borkar, Paresh M.
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US08/956,224
• Time in Patent Office: 504 Days
• Field of Search: 395/681, 395/651, 395/652, 395/653, 395/559, 395/551, 395/828, 395/830, 395/829, 395/831, 395/834
• US Class Current: 713/1
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

Configuration data indicative of interface requirements for interfacing to a host adapter card are automatically serially loaded on reset from an external device on the card into a host adapter integrated circuit on the card. A driver program can then read the configuration data from the host adapter integrated circuit and thereby determine how to interface with the host adapter card.

Claims

1. A method of loading configuration data after a reset condition into a host adapter integrated circuit from an external device, comprising:

receiving a reset signal on a first terminal of a host adapter integrated circuit, said host adapter integrated circuit being operatively coupled to a host; and

upon a deassertion of said reset signal, automatically outputting a clock signal from a second terminal of said host adapter integrated circuit to said external device such that configuration data is clocked out of said external device and into a third terminal of said host adapter integrated circuit, said reset signal remaining deasserted throughout said loading of said configuration data, said configuration data not being transferred from said host to said host adapter integrated circuit.

2. The method of claim 1, wherein the external device is taken from the group consisting of:

a ROM, a PAL, a fuse device, and an antifuse device.

3. A system, comprising:

a host;

a first storage device storing first configuration data and having a first terminal and a second terminal; and

a first host adapter integrated circuit operatively coupled to said host, said first host adapter integrated circuit outputting a clock signal to said first terminal of said first storage device such that said first configuration data from said first storage device is output from said second terminal of said first storage device and is loaded serially into said first host adapter integrated circuit, said first configuration data being indicative of a first set of interface requirements;

a second storage device storing second configuration data and having a first terminal and a second terminal; and

a second host adapter integrated circuit operatively coupled to said host, said second host adapter integrated circuit outputting a clock signal to said first terminal of said second storage device such that said second configuration data from said second storage device is output from said second terminal of said second storage device and is loaded serially into said second host adapter integrated circuit, said second configuration data being indicative of a second set of interface requirements, said first and second host adapter integrated circuits being substantially identical integrated circuits.

4. The method of claim 3, wherein the first storage device and the second storage device are taken from the group consisting of:

a ROM, a PAL, a fuse device and an antifuse device.

5. A system, comprising:

a host;

a peripheral device;

means for storing configuration data external to said host; and

a host adapter integrated circuit operatively coupled to said peripheral device via a first bus, said host adapter integrated circuit comprising;

a first terminal;

a second terminal;

a shift register having a clock input lead, a serial data input lead, and a plurality of parallel data output leads, said clock input lead being coupled to said first terminal, said serial data input lead being coupled to said second terminal, said second terminal being coupled to said means for storing configuration data such that configuration data is output from said means and onto said second terminal under control of said host adapter integrated circuit after a power up condition without said configuration data passing into or out of said host; and

a system bus interface operatively coupled to said host via a second bus.

6. The system of claim 5, wherein said host adapter integrated circuit further comprises:

a multiplexer having a plurality of first input leads, a plurality of second input leads, a plurality of output leads, and a select input lead, each of said plurality of first input leads of said multiplexer being coupled to a corresponding one of said plurality of parallel data output leads of said shift register.

7. The system of claim 6, wherein configuration data on said plurality of output leads of said multiplexer is accessible from said system bus interface.

8. The system of claim 7, wherein said host adapter integrated circuit further comprises:

a decoder having a plurality of input leads and an output lead, said plurality of input leads of said decoder being coupled to said plurality of parallel data output leads of said shift register, said output lead of said decoder being coupled to said select input lead of said multiplexer.

9. The system of claim 5, wherein said clock input lead of said shift register is coupled to said first terminal via an output buffer of said host adapter integrated circuit.

10. The system of claim 5, wherein said first terminal is an output terminal of said host adapter integrated circuit.

11. The system of claim 5, further comprising a light emitting diode (LED) coupled to said first terminal.

12. The system of claim 5, wherein said means for storing has a clock input terminal coupled to said first terminal of said host adapter integrated circuit, and wherein said means for storing has a serial data output terminal coupled to said second terminal of said host adapter integrated circuit.

13. The system of claim 5, wherein said host adapter integrated circuit further comprises:

a third terminal coupled to receive a reset signal; and

a fourth terminal coupled to receive a clock signal.

14. The system of claim 5, wherein said first bus is a SCSI bus and said second bus is a PCI bus.