Inverse modeller

• US 5,881,301 A
• Filed: 10/02/1997
• Issued: 03/09/1999
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Robbins, William Philip
• Primary Examiner(s): Donaghue, Larry D.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/947,675
• Time in Patent Office: 523 Days
• Field of Search: 395/800.01, 395/800.16, 395/800.18, 395/376, 395/377, 395/500, 395/850, 395/872, 395/888, 341/59, 358/261.1, 348/384, 348/441, 382/232
• US Class Current: 712/1
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. In a system having a data stream including run level code, the improvement characterized by:

a token formatter, accepting from the data stream first type tokens having a first predetermined width, and at least one of the following formats;

Format A--ExxxxxxLLLLLLLLLLL

Format B--ERRRRRRLLLLLLLLLLL

Format C--E000000LLLLLLLLLLL

where E=extension bit;

F=specifics format;

R=run bit;

L=length bit or non-data token;

x="don'"'"'t care" bit, said token formatter operating on said tokens by;

splitting format A tokens into a format 0a token having a form of ELLLLLLLLLLL;

splitting format B tokens into a format 1 token having the form of FRRRRRR00000 and a format 0a data token;

splitting format C tokens into a format 0 token having the form of FLLLLLLLLLLL; and

packing format 0, format 0a and format 1 tokens into a buffer, said buffer having a second predetermined width; and

inverse modeller means active upon said tokens in said buffer for expanding out said run level code to a run of zero data followed by a level, whereby each token is expressed with a specified number of values.

2. A system as recited in claim 1, wherein said token is a DATA token.

3. A system as recited in claim 1, wherein said inverse modeller means blocks tokens which lack said specified number of values.

4. A system as recited in any of claims 1-3 wherein said specified number of values is 64 coefficients.

5. A method of processing data to efficiently fill a buffer, comprising the steps of:

providing first type tokens having a first predetermined width, and at least one of the following formats;

Format A--ExxxxxxLLLLLLLLLLL

Format B--ERRRRRRLLLLLLLLLLL

Format C--E000000LLLLLLLLLLL

where E=extention bit;

F=specifics format;

R=run bit;

L=length bit or non-data token;

x="don'"'"'t care" bit;

splitting format A tokens into a format 0a token having a form of ELLLLLLLLLLL;

splitting format B tokens into a format 1 token having the form of FRRRRRR00000 and a format 0a data token;

splitting format C tokens into a format 0 token having the form of FLLLLLLLLLLL;

packing format 0, format 0a and format 1 tokens into a buffer, said buffer having a second predetermined width.

6. An apparatus for providing a time delay to a group of compressed pictures, the pictures corresponding to a video compression/decompression standard, characterized by:

words of data containing compressed pictures;

a counter circuit adapted to count said words of data;

a microprocessor in communication with said counter circuit and adapted to receive start-up information consistent with the standard of video decompression;

said microprocessor communicating said start-up information to said counter circuit;

a token formatter, accepting from the data stream first type tokens having a first predetermined width, and at least one of the following formats;

Format A--having a bit E, at least one bit L, and at least one bit x

Format B--having a bit E, at least one bit R, and at least one bit L

Format C--having a bit E, at least one bit 0, and at least one bit L,

where E=extension bit;

F=specifics format;

R=run bit;

L=length bit or non-data token;

x="don'"'"'t care" bit, said token formatter operating on said tokens by;

splitting format A tokens into a format 0a token having a bit E, at least one bit L, and no bits x;

splitting format B tokens into a format 1 token having a bit F, at least one bit R, at least one bit 0 and a said format 0a data token;

splitting format C tokens into a format 0 token having a bit F, at least one bit L, and no bits 0; and

packing format 0, format 0a and format 1 tokens into a buffer, said buffer having a second predetermined width; and

an inverse modeller circuit for accepting said words of data from said buffer and capable of delaying said words of data;

a control circuit intermediate and in communication with said counter circuit and said inverse modeller circuit;

said counter circuit comparing said start-up information with said counted words of data and signaling said control circuit; and

said control circuit queueing said signals in correspondence to said words of data that have met a start-up criterion and controlling said inverse modeller delay feature.

7. A method of processing data to efficiently fill a buffer, characterized by the steps of:

providing first type tokens having a first predetermined width, and at least one of the following formats, where E=extension bit;

F=specifics format;

R=run bit;

L=length bit or non-data token; and

x="don'"'"'t care" bit;

Format A--having a bit E, at least one bit L, and at least one bit x

Format B--having a bit E, at least one bit R, and at least one bit L

Format C--having a bit E, at least one bit 0, and at least one bit L,

said token formatter operating on said tokens by;

splitting format A tokens into a format 0a token having a bit E, at least one bit L, and no bits x;

splitting format B tokens into a format 1 token having a bit F, at least one bit R, at least one bit 0 and a said format 0a data token;

splitting format C tokens into a format 0 token having a bit F, at least one bit L, and no bits 0; and

packing format 0, format 0a and format 1 tokens into a buffer, said buffer having a second predetermined width.