Method for reducing oxidation of electroplating chamber contacts and improving uniform electroplating of a substrate

• US 5,882,498 A
• Filed: 10/16/1997
• Issued: 03/16/1999
• Est. Priority Date: 10/16/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dubin, Valery, Nogami, Takeshi
• Primary Examiner(s): Gorgos, Kathryn
• Assistant Examiner(s): Wong, Edna
• Application Number:
  US08/951,805
• Time in Patent Office: 516 Days
• Field of Search: 205/123, 205/157, 205/170, 205/181, 205/182, 205/238, 205/252, 205/261, 205/269, 205/271, 205/291, 205/184, 205/191, 438/466, 438/597
• US Class Current: 205/261
• CPC Class Codes: C23C 28/021 including at least one metal alloy layer
• CPC Class Codes: C23C 28/023 only coatings of metal elements only
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer

Abstract

A method for electroplating a silicon substrate in manufacturing a semiconductive device is provided. Electroplating process chamber contacts or fingers used in positioning a silicon substrate or wafer during an electroplating process are plated with a metal layer to prevent oxidation of the contacts. Oxidation of the contacts may result in increased and varying resistance of the contacts and thus nonuniform plating of the silicon wafer and possibly even deplating of a seed layer. A 20 mA/cm² current is applied to the contacts which are immersed in an electrolyte solution before loading a silicon wafer. A silicon wafer is then loaded into the electroplating process chamber containing the electrolyte solution. The preplating of the contacts enables the formation of a uniform metal layer on the silicon substrate. Additionally, voltage then may be applied to the contacts after unloading the silicon wafer to reduce oxidation. This electroplating method reduces expensive maintenance time in replacing or cleaning electroplating chamber contacts. The method also does not require expensive and complex electronics to monitor and supply current to the contacts.

Claims

1. A method for electroplating a substrate, comprising the steps of:

(a) immersing a contact for positioning the substrate into an electrolyte solution;

(b) applying a first current amount to the contact for plating only the contact with a metal layer;

(c) positioning the substrate with the plated contact in the electrolyte solution; and

(d) applying a second current amount to the substrate for forming a metal layer on the substrate.

2. The method of claim 1, wherein the metal layer on the contact and the substrate is copper.

3. The method of claim 1, wherein the metal layer on the contact and the substrate is nickel.

4. The method of claim 1, wherein the metal layer on the contact and the substrate is cobalt.

5. The method of claim 1, wherein the metal layer on the contact and the substrate is tin-lead (SnPb) alloy.

6. The method of claim 1, wherein the first current amount is approximately 20 mA/cm².

7. The method of claim 2, wherein the copper layer on the substrate is approximately 1.5 μ

m thick.

8. The method of claim 2, wherein the copper is uniform within approximately 5%.

9. The method of claim 1 wherein the substrate is an approximately 8" silicon wafer.

10. The method of claim 9, wherein the silicon wafer includes a trench having a barrier layer and a seed layer.

11. The method of claim 1, further including the steps of:

(e) removing the contact and substrate from the electrolyte solution;

(f) removing the substrate from the contact;

(g) immersing the contact into the electrolyte solution; and

,

(h) applying less than approximately 15 mA/cm² to the contact.

12. The method of claim 1, further including the steps of:

(e) removing the contact and substrate from the electrolyte solution;

(f) removing the substrate from the contact; and

,

(g) applying approximately 1.5 to approximately 2.0 V to the contact.

13. A method for electroplating a silicon wafer with a copper layer using an electroplating process chamber having a plurality of contacts and containing a copper electrolyte solution, comprising the steps of:

(a) immersing the plurality of contacts into the copper electrolyte solution;

(b) applying an approximately 20 mA/cm² current to the plurality of contacts for plating only the plurality of contacts with a layer of copper;

(c) removing the plurality of copper plated contacts from the copper electrolyte solution;

(d) positioning the silicon wafer on the plurality of copper plated contacts;

(e) immersing the plurality of copper plated contacts and silicon wafer into the electrolyte solution; and

,

(f) applying a current to the plurality of copper plated contacts for plating the silicon wafer with the layer of copper.

14. The method of claim 13, further including the steps of:

(g) removing the plurality of contacts and the silicon wafer from the electrolyte solution;

(h) immersing the plurality of contacts into the electrolyte solution; and

,

(i) applying an approximately less than 15 mA/cm² current to the plurality of contacts.

15. The method of claim 13, further including the steps of:

(g) removing the plurality of contacts and the silicon wafer from the electrolyte solution;

(h) removing the silicon wafer from the contacts; and

,

(i) applying a voltage of approximately 1.5 to approximately 2.0 V to the plurality of contacts.

16. The method of claim 13, wherein the method further includes the steps of:

(g) forming a trench in an interlevel dielectric in the silicon wafer;

(h) forming a tantalum layer on the silicon wafer; and

,

(i) forming a copper seed layer on the tantalum layer.

17. The method of claim 16, wherein the copper seed layer is approximately 100 nm thick.

18. The method of claim 16, wherein the tantalum layer is approximately 30 nm thick.

19. The method of claim 13, wherein the plurality of contacts includes 6 contacts.

20. The method of claim 13, wherein the copper layer of the silicon wafer is uniform within approximately 5%, 1 sigma.

21. The method of claim 13, wherein the silicon wafer is an approximately 8" silicon wafer.