High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
First Claim
Patent Images
1. In combination:
- an insulating substrate;
a layer of silicon formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said silicon layer to temperatures of less than or equal to approximately 950°
C. during any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment; and
a logic component fabricated in said silicon layer wherein said logic component is selected from the group including a NAND gate, a NOR gate and a transmission gate.
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Abstract
A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.
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Citations
26 Claims
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1. In combination:
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an insulating substrate; a layer of silicon formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said silicon layer to temperatures of less than or equal to approximately 950°
C. during any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment; anda logic component fabricated in said silicon layer wherein said logic component is selected from the group including a NAND gate, a NOR gate and a transmission gate. - View Dependent Claims (2, 3, 4, 5)
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6. An electronic memory comprising:
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an insulating substrate; a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°
C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate; a first P-channel transistor fabricated in said layer of silicon formed on said insulating substrate; a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate; a second P-channel transistor fabricated in said layer of silicon formed on said insulating substrate, wherein said first N-channel transistor, said first P-channel transistor, said second N-channel transistor and said second P-channel transistor are interconnected to form a cross coupled inverter; and a transmission gate electrically connected to said cross coupled inverter wherein said transmission gate comprises either one of a third P-channel transistor or a third N-channel transistor fabricated in said layer of silicon formed on said insulating substrate.
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7. A microelectronic circuit comprising:
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an electrically insulating substrate; a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×
1011 cm-2 achieved by controlling the temperature of said semiconductive silicon layer to temperatures of less than or equal to approximately 950°
C. during any processing of said semiconductive silicon layer which exposes said semiconductive silicon layer to a non-oxidizing ambient environment; anda field effect transistor formed in the semiconductive silicon layer. - View Dependent Claims (8, 9)
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10. An electronic memory circuit comprising:
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an electrically insulating substrate; a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×
1011 cm-2 achieved by controlling the temperature of said semiconductive silicon layer to temperatures of less than or equal to approximately 950°
C. during any processing of said semiconductive silicon layer which exposes said semiconductive silicon layer to a non-oxidizing ambient environment;a first N-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate; a first P-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate; a second N-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate; and a second P-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate, wherein said first N-channel transistor, said first P-channel transistor, said second N-channel transistor and said second P-channel transistor are interconnected to form a flip-flop circuit element. - View Dependent Claims (11)
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12. A MOS device comprising:
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an insulating substrate; a silicon layer formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said silicon layer to temperatures of less than or equal to approximately 950°
C. during any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment;a source region formed in said silicon layer; a drain region formed in said silicon layer; a channel region formed in said silicon layer between said source region and said drain region; and a gate positioned adjacent said channel region. - View Dependent Claims (13, 14, 15, 16)
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17. A NAND gate comprising:
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an insulating substrate; a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°
C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;first and second P-channel transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second P-channel transistors have widths of less than approximately 1.3 μ
m and lengths of less than approximately 0.7 μ
m;a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate wherein said first N-channel transistor has a width of less than approximately 0.9 μ
m and a length of less than approximately 0.8 μ
m; anda second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate wherein said second N-channel transistor has a width of less than approximately 1.0 μ
m and a length of less than approximately 0.8 μ
m.
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18. A NOR gate comprising:
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an insulating substrate; a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°
C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;first and second PMOS transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second PMOS transistors have widths of less than approximately 1.5 μ
m and lengths of less than approximately 0.7 μ
m; andfirst and second NMOS transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second NMOS transistors have widths of less than approximately 1.0 μ
m and lengths of less than approximately 0.8 μ
m.
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19. A logic component comprising:
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an insulating substrate; a layer of silicon formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°
C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate; a first P-channel transistor fabricated in said layer of silicon formed on said insulating substrate; a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate; and a second P-channel transistor fabricated in said layer of silicon formed on said insulating substrate, wherein said first N-channel transistor, said first P-channel transistor, said second N-channel transistor and said second P-channel transistor are interconnected to form a flip-flop element. - View Dependent Claims (20)
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21. A logic component comprising:
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an insulating substrate; a layer of silicon formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°
C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate; a first resistor fabricated in said layer of silicon formed on said insulating substrate; a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate; and a second resistor fabricated in said layer of silicon formed on said insulating substrate, wherein said first N-channel transistor, said first resistor, said second N-channel transistor and said second resistor are interconnected to form a flip-flop element. - View Dependent Claims (22)
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23. A MOS device comprising:
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an insulating substrate; a silicon layer formed on said sapphire substrate wherein said silicon layer is less than approximately 1000 Å
thick and is substantially free of electrically active states achieved by controlling the temperature of said silicon layer to temperatures of less than or equal to approximately 950°
C. during any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment;a source region formed in said silicon layer, wherein a voltage VS is applied to said source region; a drain region formed in said silicon layer, wherein a voltage VD is applied to said drain region; a channel region formed in said silicon layer between said source region and said drain region; and a gate positioned adjacent said channel region, wherein a voltage VG is applied to said source region to control current flowing between said source and said drain, IDS. - View Dependent Claims (24, 25)
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26. A digital electronic circuit comprising:
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an electrically insulating substrate; a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×
1011 cm-2 achieved by controlling the temperature of said semiconductive silicon layer to temperatures of less than or equal to approximately 950°
C. during any processing of said semiconductive silicon layer which exposes said semiconductive silicon layer to a non-oxidizing ambient environment; anda digital field effect transistor element that is formed in the semiconductive silicon layer and includes; an N-type source; an N-type drain; and a P-type channel having a gate length of less than approximately 0.8 micrometers, negligible source-body effect and a mobility higher than approximately 180 cm/volt-second; and a gate formed over the channel.
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Specification