High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

• US 5,883,396 A
• Filed: 10/17/1996
• Issued: 03/16/1999
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/733,320
• Time in Patent Office: 880 Days
• Field of Search: 257/9, 257/213, 257/280, 257/327, 257/347, 257/350, 257/369
• US Class Current: 257/9
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS
• CPC Class Codes: Y10S 438/967 Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Claims

1. In combination:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said silicon layer to temperatures of less than or equal to approximately 950°

C. during any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment; and

a logic component fabricated in said silicon layer wherein said logic component is selected from the group including a NAND gate, a NOR gate and a transmission gate.

2. The combination defined in claim 1 wherein said insulating substrate comprises sapphire.

3. The combination defined in claim 1 wherein said layer of silicon has an areal density of electrically active states which is less than approximately 5×

10¹¹ cm^-2.

4. The combination defined in claim 1 wherein said logic component selected from the group including a NAND gate, a NOR gate and a transmission gate further comprises P-channel transistors and N-channel transistors fabricated in said layer of silicon formed on said insulating substrate.

5. The combination defined in claim 4 wherein said logic component comprises CMOS FET transistors.

6. An electronic memory comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;

a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate;

a first P-channel transistor fabricated in said layer of silicon formed on said insulating substrate;

a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate;

a second P-channel transistor fabricated in said layer of silicon formed on said insulating substrate, wherein said first N-channel transistor, said first P-channel transistor, said second N-channel transistor and said second P-channel transistor are interconnected to form a cross coupled inverter; and

a transmission gate electrically connected to said cross coupled inverter wherein said transmission gate comprises either one of a third P-channel transistor or a third N-channel transistor fabricated in said layer of silicon formed on said insulating substrate.

7. A microelectronic circuit comprising:

an electrically insulating substrate;

a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×

10¹¹ cm^-2 achieved by controlling the temperature of said semiconductive silicon layer to temperatures of less than or equal to approximately 950°

C. during any processing of said semiconductive silicon layer which exposes said semiconductive silicon layer to a non-oxidizing ambient environment; and

a field effect transistor formed in the semiconductive silicon layer.

8. A circuit as in claim 7 in which the electrically insulating substrate comprises sapphire.

9. A circuit as in claim 7 in which the field effect transistor has a gate length of less than approximately 0.8 micrometers.

10. An electronic memory circuit comprising:

an electrically insulating substrate;

a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×

10¹¹ cm^-2 achieved by controlling the temperature of said semiconductive silicon layer to temperatures of less than or equal to approximately 950°

C. during any processing of said semiconductive silicon layer which exposes said semiconductive silicon layer to a non-oxidizing ambient environment;

a first N-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate;

a first P-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate;

a second N-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate; and

a second P-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate, wherein said first N-channel transistor, said first P-channel transistor, said second N-channel transistor and said second P-channel transistor are interconnected to form a flip-flop circuit element.

11. A circuit as in claim 10 in which the memory element further comprises a transmission gate electrically connected to said flip-flop circuit element wherein said transmission gate comprises either one of a third P-channel transistor or a third N-channel transistor fabricated in said semiconductive silicon layer formed on said insulating substrate.

12. A MOS device comprising:

an insulating substrate;

a silicon layer formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said silicon layer to temperatures of less than or equal to approximately 950°

C. during any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment;

a source region formed in said silicon layer;

a drain region formed in said silicon layer;

a channel region formed in said silicon layer between said source region and said drain region; and

a gate positioned adjacent said channel region.

13. A MOS device as defined in claim 12 wherein said insulating substrate comprises sapphire.

14. A MOS device as defined in claim 12 wherein said silicon layer has an areal density of electrically active states which is less than approximately 5×

10¹¹ cm^-2.

15. A MOS device as defined in claim 12 wherein said channel has a length of less than approximately 0.8 μ

m.

16. A MOS device as defined in claim 12 wherein said source region and said drain region overlap said gate by less than approximately 0.06 μ

m.

17. A NAND gate comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;

first and second P-channel transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second P-channel transistors have widths of less than approximately 1.3 μ

m and lengths of less than approximately 0.7 μ

m;

a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate wherein said first N-channel transistor has a width of less than approximately 0.9 μ

m and a length of less than approximately 0.8 μ

m; and

a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate wherein said second N-channel transistor has a width of less than approximately 1.0 μ

m and a length of less than approximately 0.8 μ

m.

18. A NOR gate comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;

first and second PMOS transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second PMOS transistors have widths of less than approximately 1.5 μ

m and lengths of less than approximately 0.7 μ

m; and

first and second NMOS transistors fabricated in said layer of silicon formed on said insulating substrate wherein said first and second NMOS transistors have widths of less than approximately 1.0 μ

m and lengths of less than approximately 0.8 μ

m.

19. A logic component comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;

a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate;

a first P-channel transistor fabricated in said layer of silicon formed on said insulating substrate;

a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate; and

a second P-channel transistor fabricated in said layer of silicon formed on said insulating substrate, wherein said first N-channel transistor, said first P-channel transistor, said second N-channel transistor and said second P-channel transistor are interconnected to form a flip-flop element.

20. A logic component as defined in claim 19 further comprising a transmission gate electrically connected to said flip-flop element wherein said transmission gate comprises either one of a third P-channel transistor or a third N-channel transistor fabricated in said layer of silicon formed on said insulating substrate.

21. A logic component comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said silicon layer is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;

a first N-channel transistor fabricated in said layer of silicon formed on said insulating substrate;

a first resistor fabricated in said layer of silicon formed on said insulating substrate;

a second N-channel transistor fabricated in said layer of silicon formed on said insulating substrate; and

a second resistor fabricated in said layer of silicon formed on said insulating substrate, wherein said first N-channel transistor, said first resistor, said second N-channel transistor and said second resistor are interconnected to form a flip-flop element.

22. A logic component as defined in claim 21 further comprising a transmission gate electrically connected to said flip-flop element wherein said transmission gate comprises either one of a first P-channel transistor or a third N-channel transistor fabricated in said layer of silicon formed on said insulating substrate.

23. A MOS device comprising:

an insulating substrate;

a silicon layer formed on said sapphire substrate wherein said silicon layer is less than approximately 1000 Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said silicon layer to temperatures of less than or equal to approximately 950°

C. during any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment;

a source region formed in said silicon layer, wherein a voltage V_S is applied to said source region;

a drain region formed in said silicon layer, wherein a voltage V_D is applied to said drain region;

a channel region formed in said silicon layer between said source region and said drain region; and

a gate positioned adjacent said channel region, wherein a voltage V_G is applied to said source region to control current flowing between said source and said drain, I_DS.

24. A MOS device as defined in claim 23 wherein said current flowing through said channel from said source to said drain, I_DS, is a linear function of the voltage difference between said source and said drain, V_D -V_S =V_DS.

25. A MOS device as defined in claim 23 wherein said channel is fully depleted.

26. A digital electronic circuit comprising:

an electrically insulating substrate;

a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×

10¹¹ cm^-2 achieved by controlling the temperature of said semiconductive silicon layer to temperatures of less than or equal to approximately 950°

C. during any processing of said semiconductive silicon layer which exposes said semiconductive silicon layer to a non-oxidizing ambient environment; and

a digital field effect transistor element that is formed in the semiconductive silicon layer and includes;

an N-type source;

an N-type drain; and

a P-type channel having a gate length of less than approximately 0.8 micrometers, negligible source-body effect and a mobility higher than approximately 180 cm/volt-second; and

a gate formed over the channel.