Thin film transistor having double channels and its manufacturing method

• US 5,883,399 A
• Filed: 07/08/1997
• Issued: 03/16/1999
• Est. Priority Date: 12/26/1994
• Status: Expired due to Fees

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Yun Ki, Yin, Sung Wook
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/893,544
• Time in Patent Office: 616 Days
• Field of Search: 257/241, 257/244, 257/249, 257/266, 257/330-333, 257/397, 257/66, 257/71, 257/287, 257/347, 438/151, 438/149, 438/158, 438/259
• US Class Current: 257/66
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

This invention provides a method for manufacturing a this film transistor which comprised the steps of providing an oxide layer; etching a portion of the oxide layer so that a recess is formed; forming a first channel layer on the resulting structure; forming a first gate oxide layer on the first channel layer in a portion including the recess region; forming a polysilicon layer on the resulting structure, filling in the recess region; etching back the polysilicon layer until the surface of a portion of the first gate oxide layer, leaving the residual layer on the first channel layer, which is exposed by the first gate oxide layer, wherein the surface of the resulting structure has uniform topology by the etching process; forming a second gate oxide layer on the polysilicon layer; forming a second channel layer on the resulting structure; and implanting impurity ions for forming source/drain regions, whereby the source/drain region consists of multi-layers, the first channel layer, the second polysilicon layer and the second channel layer.

Claims

1. A thin film transistor having double channels, comprising:

an insulating layer;

a first channel layer formed on said insulating layer;

a first gate insulating layer partially formed on said first channel layer;

a gate electrode partially formed on said first gate insulating layer;

a second gate insulating layer formed on said gate electrode;

a polysilicon layer partially formed on each end of the first channel layer; and

a second channel layer formed on said second gate insulating layer and the polysilicon layer, wherein said second channel layer is electrically connected with said first channel layer through the polysilicon layer such that each end of the channel layers consisted of the first channel layer, the polysilicon layer and the second channel layer is thicker than the channel layers so that the on-current is increased.

2. A thin film transistor according to claim 1, wherein said insulating layer has a recess.

3. A thin film transistor according to claim 2, wherein said gate electrode is formed in the recess.

4. A thin film transistor according to claim 2, wherein said gate electrode is polysilicon which fills the recess.

5. A thin film transistor according to claim 1, wherein said first and second channels constitute a first and second current paths, respectively.

6. A thin film transistor according to claim 5, wherein the first current path is formed beneath said first gate insulating layer.

7. A thin film transistor according to claim 5, wherein the second current path is formed above said second gate insulating layer.

8. A thin film transistor according to claim 1, wherein said first and second gate insulating layers are oxide layers.

9. A thin film transistor according to claim 1, wherein one end of said first and second channel layers forms a drain region and the other end of said first and second channel layers forms a source region of said transistor.

10. A thin film transistor according to claim 9, wherein an upper surface of a resulting structure comprised of said source and drain regions, said gate electrode and said first gate insulating layer has uniform topology.

11. A thin film transistor according to claim 1, wherein said first and second channel layers are polysilicon layers.

12. A thin film transistor comprising:

an insulating layer having a recess; and

a transistor formed on said insulating layer, said transistor having first and second current paths, wherein a gate electrode of said transistor is formed in said recess, said transistor comprising;

a first channel layer formed on said insulating layer;

a first gate insulating layer formed on said first channel layer such that said first channel layer forms said first current path beneath said first gate insulating layer;

a second gate insulating layer formed on said gate electrode; and

a second channel layer formed on said second gate insulating layer such that said second gate insulating layer forms said second current path above said second gate insulating layer.

13. A thin film transistor according to claim 12, wherein said first and second channel layers are polysilicon layers.

14. A thin film transistor according to claim 12, wherein an upper surface of a resulting structure comprised of said source and drain regions, said gate electrode and said first gate insulating layer has uniform topology.

15. A thin film transistor according to claim 12, wherein said first and second gate insulating layers are oxide layers.

16. A thin film transistor according to claim 12, wherein one end of said first and second channel layers forms a drain region and the other end of said first and second channel layers forms a source region of said transistor.