FPGA architecture with repeatable titles including routing matrices and logic matrices

• US 5,883,525 A
• Filed: 10/03/1997
• Issued: 03/16/1999
• Est. Priority Date: 04/01/1994
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Yee, Wilson K., Holen, Victor A., Tavana, Danesh
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/943,890
• Time in Patent Office: 529 Days
• Field of Search: 326/39, 326/40, 326/41
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.

Claims

1. An interconnect structure comprising:

a plurality of signal lines;

a first plurality of transistors, each transistor provided on one signal line;

at least one memory device for controlling the state of said plurality of transistors;

a second plurality of transistors, each transistor coupled to a subset of said first plurality of transistors; and

a decoder for controlling the states of said second plurality of transistors, wherein said decoder determines which of said second plurality of transistors provides a signal on an output line.

2. The interconnect structure of claim 1 further comprising a third plurality of transistors coupled in series to one subset of said first plurality transistors.

3. The interconnect structure of claim 2 wherein said at least one memory device includes a plurality of memory devices, and wherein each memory device controls the state of one of said third plurality of transistors.

4. The interconnect structure of claim 3 wherein said plurality of memory devices provide a signal to said first plurality of transistors and the complement of said signal to said third plurality of transistors.

5. An interconnect structure comprising:

a plurality of lines;

a first plurality of transistors, each transistor provided on one signal line;

a first memory device for controlling the state of said first plurality of transistors, wherein said means for controlling provides a signal to a first group of said first plurality of transistors and provides the complement of said signal to a second group of said first plurality of transistors;

a second plurality of transistors, each transistor coupled to a subset of said first plurality of transistors;

a second memory device for controlling the state of said second plurality of transistors, wherein said means for controlling provides a signal to a first group of said second plurality of transistors and provides the complement of said signal to a second group of said second plurality of transistors;

a third plurality transistors, each transistor coupled to a subset of said second plurality of transistors;

a third memory device for controlling the state of said third plurality of transistors, wherein said means for controlling provides a signal to a first group of said third plurality of transistors and provides the complement of said signal to a second group of said third plurality of transistors, wherein one of said third plurality of transistors provides a signal on an output line.