Power-on reset circuit based upon FET threshold level
First Claim
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1. A power-on reset circuit for circuitry that is powered by a supply voltage Vdd, comprising:
- an initiation circuit having an output state that initiates a reset signal when Vdd rises above a reset initiation level; and
a reset termination circuit that includes p-channel and n-channel FETs characterized by respective threshold voltages Vtp and Vtn and that is connected to alter the output state of said initiation circuit so as to terminate said reset signal in response to Vdd reaching a termination threshold that is substantially greater than said reset initiation level, said reset termination circuit comprising a pair of said p-channel and n-channel FETs with their sources and gates cross-coupled and their source-drain circuits connected in series between high and low power supply terminals.
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Abstract
A power-on reset circuit initiates a reset signal when the circuit'"'"'s power supply voltage is low, and terminates the signal in response to the supply voltage exceeding a reset termination threshold that is based upon the greater of the threshold voltages for p-channel and n-channel FETs employed in the circuit. The reset termination threshold is preferably the sum of the greater FET threshold plus a safety margin, with the termination delayed by a predetermined period to ensure an adequate reset period, and a hysteresis feature added to ensure a stable reset termination.
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Citations
18 Claims
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1. A power-on reset circuit for circuitry that is powered by a supply voltage Vdd, comprising:
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an initiation circuit having an output state that initiates a reset signal when Vdd rises above a reset initiation level; and a reset termination circuit that includes p-channel and n-channel FETs characterized by respective threshold voltages Vtp and Vtn and that is connected to alter the output state of said initiation circuit so as to terminate said reset signal in response to Vdd reaching a termination threshold that is substantially greater than said reset initiation level, said reset termination circuit comprising a pair of said p-channel and n-channel FETs with their sources and gates cross-coupled and their source-drain circuits connected in series between high and low power supply terminals. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A power-on reset circuit for circuitry supplied with power from high and low power terminals, comprising:
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a reset initiation circuit connected to produce an output state which initiates a reset pulse, and cross-coupled n-channel and p-channel field effect transistors (FETs) connected in series between said high and low power terminals so that both of said FETs conduct in response to the voltage across their series connection exceeding the greater of the p-channel and n-channel FET thresholds Vtp and Vtn, respectively, said FETs being further connected to alter the output state of said reset initiation circuit when they conduct so as to terminate said reset pulse. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A digital to analog converter (DAC) which derives power from a power source having a supply voltage Vdd, comprising:
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a digital circuit section including CMOS circuitry composed of p-channel and n-channel field effect transistors (FETs) characterized by respective threshold voltages Vtp and Vtn, said digital circuit section connected to receive digital data, an analog output section connected to produce analog output signals corresponding to the digital value of said digital data, an initiation circuit having an output state that initiates a reset signal that resets said digital circuit section when Vdd rises above a reset initiation level less than the greater of Vtp and Vtn, and a reset termination circuit that includes p-channel and n-channel FETs with their sources and gates cross-coupled and their source-drain circuits connected in series between high and low power supply terminals, said FETs characterized by said respective threshold voltages Vtp and Vtn, and that is connected to alter the output state of said initiation circuit so as to terminate said reset signal in response to Vdd reaching a power-on threshold that is at least equal to the greater of Vtp and Vtn. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification