Charging of a bootstrap capacitance through an LDMOS

• US 5,883,547 A
• Filed: 05/13/1996
• Issued: 03/16/1999
• Est. Priority Date: 05/17/1995
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Diazzi, Claudio, Tarantola, Mario, Martignoni, Fabrizio
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US08/644,449
• Time in Patent Office: 1,037 Days
• Field of Search: 327/427, 327/325, 327/375, 327/378, 327/534, 327/537, 327/390, 327/589
• US Class Current: 327/589
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches

Abstract

A charging circuit for a bootstrap capacitance employing an integrated LDMOS transistor and including a circuital device for preventing the turning on a parasitic transistors of the integrated LDMOS structure during transients that comprises a plurality of directly biased junctions (D1, D2, . . . , Dn) connected in series between a source and a body of the LDMOS transistor structure and at least a current generator, tied to ground potential, coupled between said body and ground, has at least one switch (INT1) between said source and a first junction (D1) of said plurality of junctions and a limiting resistance (R) connected between the body and the current generator (GEN). The switch (INT1) is kept open during a charging phase of the bootstrap capacitance (Cboot) and is closed when the charge voltage (Vboot) of the bootstrap capacitance reaches a preset threshold. Moreover, the body voltage (VB) is prevented from exceeding the source voltage (VS) plus a Vbe, by controlling a discharge path (T2) with a control stage (T1, R1) in response to a drop of the voltage on the limiting resistance (R). This body voltage control circuit is enabled by a second switch (INT2) driven in phase with the first switch (INT1).

Claims

1. A charging circuit for a bootstrap capacitance having a circuit for charging the bootstrap capacitor including an integrated LDMOS transistor;

and a circuital device for preventing the turning on of a parasitic transistor of the LDMOS structure during transients comprising;

a predetermined number of p-n junction diodes positioned between a source node and a body node of the LDMOS transistor;

at least a current generator connected to the ground potential of the circuit and functionally connected between said body node and a ground node, at least one switch connected between said source node and a first junction of said predetermined number of p-n junction diodes, a limiting resistance connected between said body node and said current generator, and switch controlling means connected to said at least one switch for opening said at least one switch during a charging phase of said bootstrap capacitance and for closing said at least one switch when a charge voltage of the bootstrap capacitance reaches a predetermined threshold.

2. A charging circuit according to claim 1, wherein the predetermined threshold is greater or equal to a source voltage of the LDMOS minus the product of the predetermined number of diodes plus one times a base-emitter voltage of the parasitic transistor.

3. A charging circuit according to claim 1, further comprising a circuit capable of preventing the body voltage from exceeding the source voltage plus a base-emitter voltage of the parasitic transistor, by establishing a discharge path of said body enabled by a control stage in response to a voltage drop detected on said limiting resistance.

4. A charging circuit according to claim 3, wherein said at least one switch comprises a first switch, and wherein said control stage comprises a second enabling switch which is driven in phase with said first switch.

5. A charging circuit according to claim 4, wherein said first switch is driven by a control circuit responding to the charge voltage of the bootstrap capacitance.

6. A charging circuit according to claim 5, wherein said control circuit comprises a comparator, a level shifter circuit driven by the output of said comparator and capable of forcing a current through a resistance connected between the output node of said level shifter circuit and a ground node;

one logic NAND gate having a first input coupled to said resistance, a second input controlled by an enabling logic signal and an output coupled to a control terminal of said first switch.

7. A charging circuit according to claims 6, wherein the output of said logic NAND gate is coupled to the control terminals of said first and second switches.

8. An integrated circuit, comprising:

a bootstrap capacitor;

an LDMOS transistor connected to said bootstrap capacitor, said LDMOS transistor having a body node, a source node, a parasitic PNP transistor, and a parasitic NPN transistor;

a plurality of diodes located between said source node and said body node;

a current generator connected to at least one of said plurality of diodes and a ground potential and also connected between said body node and the ground potential;

a resistor connected to said body node and said current generator;

a switch located between said source node and one of said plurality of diodes; and

control circuitry connected to open said switch when charging said bootstrap capacitor, and close said switch when the voltage of said bootstrap capacitor reaches a predetermined threshold;

wherein the voltage of said body node increases when said switch is closed, without turning on either of said parasitic transistors.

9. An integrated circuit, comprising:

a bootstrap capacitor;

an LDMOS transistor connected to said bootstrap capacitor, said LDMOS transistor having a body node, a source node, a parasitic PNP transistor, and a parasitic NPN transistor,

a plurality of diodes located between said source node and said body node;

a current generator connected to at least one of said plurality of diodes and a ground potential and also connected between said body node and the ground potential;

a resistor connected to said body node and to one of said plurality of diodes;

a switch located between said source node and one of said plurality of diodes; and

control circuitry connected to open said switch when charging said bootstrap capacitor, and close said switch when the voltage of said bootstrap capacitor reaches a predetermined threshold;

wherein the voltage of said body node rises when said switch is closed, without turning on either of said parasitic transistors;

whereby said resistor functions as a current limiter when said switch prematurely closes.

10. An integrated circuit, comprising:

a bootstrap capacitor;

an LDMOS transistor connected to said bootstrap capacitor, said LDMOS transistor having a body node, a source node;

a parasitic PNP transistor, and a parasitic NPN transistor;

a plurality of diodes located between said source node and said body node;

a current generator connected to at least one of said plurality of diodes and a ground potential and also connected between said body node and the ground potential;

a resistor connected to said body node and to one of said plurality of diodes;

a driving stage connected to said bootstrap capacitor, wherein said bootstrap capacitor biases said driving stage when said driving stage is driven in a turn-on mode;

a switch located between said source node and one of said plurality of diodes; and

control circuitry connected to open said switch when charging said bootstrap capacitor, and close said switch when the voltage of said bootstrap capacitor reaches a predetermined threshold;

wherein a voltage of said body node rises when said switch is closed, without turning on either of said parasitic transistors;

whereby a supply of said driving stage is ensured by said bootstrap capacitor.

11. The integrated circuit of claim 10, wherein said driving stage comprises a high side driver.

12. An integrated circuit, comprising:

a bootstrap capacitor;

an LDMOS transistor connected to said bootstrap capacitor, said LDMOS transistor having a body node, a source node, a parasitic PNP transistor, and a parasitic NPN transistor;

a plurality of forward biased diodes located between said source node and said body node;

a current generator connected to at least one of said plurality of diodes and a ground potential and also connected between said body node and the ground potential;

a first resistor connected to said body node and one of said plurality of forward biased diodes;

a first switch located between said source node and one of said plurality of forward biased diodes;

discharge circuitry comprising a discharge path of said body node through a first transistor, and a driving stage, said discharge path being controlled by said driving stage, said driving stage being connected in response to the voltage drop across said resistor;

a second switch driven in phase with said first switch, said discharge circuitry being enabled by said second switch; and

control circuitry connected to open said first and second switches when charging said bootstrap capacitor and to close said first and second switches when a voltage of said bootstrap capacitor reaches a predetermined threshold;

wherein a voltage of said body node rises when said first switch is closed, without turning on either of said parasitic transistors;

wherein said second switch enables said driving stage when the capacitance of said bootstrap capacitor reaches a desired charge;

whereby said second switch functions as a current limiter when said first switch prematurely closes.

13. The integrated circuit of claim 12, wherein said driving stage comprises a second transistor and a second resistor, wherein said second transistor turns on said first transistor when said second switch is closed.

14. The integrated circuit of claim 12, wherein said control circuitry further comprises a comparator connected to sense the voltage of said bootstrap capacitor.

15. A method for charging a bootstrap capacitor, comprising the steps of:

providing an LDMOS transistor connected to said bootstrap capacitor, said LDMOS transistor having a body node, a source node, a parasitic PNP transistor, and a parasitic NPN transistor;

providing a current generator connected to said body node of said LDMOS and a ground potential;

connecting a plurality of diodes between said source node and said body node;

connecting a resistor between said body node and at least one of said plurality of diodes;

providing a switch located between said source node and one of said plurality of diodes;

opening said switch when charging said bootstrap capacitor; and

closing said switch when the voltage of said bootstrap capacitor reaches a predetermined threshold;

wherein a voltage of said body node rises when said switch is closed, without turning on either of said parasitic transistors.