Method and apparatus for reading/writing data in a memory system including programmable resistors

• US 5,883,827 A
• Filed: 08/26/1996
• Issued: 03/16/1999
• Est. Priority Date: 08/26/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Morgan, Donald M.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/704,953
• Time in Patent Office: 932 Days
• Field of Search: 365/100, 365/63, 365/148, 365/189.06, 365/189.07, 365/189.09
• US Class Current: 365/100
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0047 Read destroying or disturbing the data
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

The present invention relates to circuitry and a related method to reliably write data to an array of programmable resistance elements by selectively applying pulses of a sufficient level to impart either a first (high) or second (low) resistance state to selected programmable resistance elements to store either a binary "1" or "0", respectively. Data is then read from the array by supplying currents though the selected programmable resistance element and a fixed resistive element. A comparison of the resulting voltages on nodes coupled to these resistive elements will indicate whether the resistance value of the programmable resistance element is at a high or low state, i.e., a binary "1" or "0". Further, a shunt circuit is coupled to the selected column lines of the array to protect the programmable resistance elements from excessive spurious or noise currents, which can erroneously program the programmable resistance elements.

Claims

1. A memory system comprising:

an array of programmable resistance elements, each of which being programmable to one of a first resistance state and a second resistance state, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array;

a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate read-out signals in response to said comparisons;

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;

a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows;

a column decoder circuit coupled to select one of said column lines; and

a row decoder circuit coupled to select one of said row lines, thereby selecting one of said programmable resistance elements coupled to said selected column line and said selected row line.

2. A memory system in accordance with claim 1, wherein said column decoder has a plurality of outputs respectively corresponding to said plurality of column lines, one of said plurality of outputs operable to select said selected column line.

3. A memory system in accordance with claim 2, wherein said column decoder circuit further comprises:

a plurality of driver circuits respectively coupled to said plurality of outputs of said column decoder, one of said plurality of driver circuits coupled to said one output and generating a first potential signal operable to select said selected column line, remaining ones of said plurality of driver circuits receiving a second potential signal and supplying, in response thereto, a third potential signal to said remaining outputs of said column decoder, thereby deselecting said column lines other than said selected column line.

4. A memory system in accordance with claim 3, wherein a magnitude of said first potential signal being greater than a magnitude of said second potential signal.

5. A memory system in accordance with claim 3, wherein each said plurality of driver circuits includes an inverter circuit.

6. A memory system in accordance with claim 3, wherein each of said plurality of driver circuits respectively includes:

a n-channel MOS transistor having a source electrode for connection to a ground potential, a gate electrode for receiving an input signal, and a drain electrode coupled to said output node of said first driver circuit;

a first p-channel MOS transistor having a drain electrode coupled to said gate electrode of said n-channel transistor, a source electrode coupled to a supply potential, and a gate electrode coupled to said driver circuit output; and

a second p-channel MOS transistor having a drain electrode coupled to a drain electrode of said n-channel MOS transistor, a source electrode coupled to said supply potential, and a gate electrode coupled to said drain electrode of said first p-channel MOS transistor,

wherein said supply potential is greater than said magnitude of said second potential signal.

7. A memory system in accordance with claim 1, wherein said sense signals include sense voltages developed by directing a sense current through said programmable resistance elements and said reference signals include reference voltages derived from a reference current.

8. A memory system in accordance with claim 7, further comprising:

a first comparison circuit input line coupled to said selected one of said column lines, said sense current flowing through said first comparison circuit input line and through said selected one of said programmable resistance elements; and

a second comparison circuit input line for conducting said reference current.

9. A memory system in accordance with claim 8, wherein said comparison circuit comprises:

an amplifier circuit having first and second sense nodes respectively coupled to said first and second comparison input lines, respectively.

10. A memory system in accordance with claim 7, wherein said sense voltage and said reference voltage are generated on said first and second comparison circuit input lines, respectively, and

when said sense voltage is greater than said reference voltage, said amplifier circuit drives said first sense node to a voltage higher than said sense voltage and drives said second sense node to a voltage less than said reference voltage, and

when said sense voltage is less than said reference voltage, said amplifier circuit drives said first sense node to a voltage less than said sense voltage and drives said second sense node to a voltage higher than said reference voltage, said voltages on said first and second sense nodes are supplied to first and second output nodes of said amplifier, respectively.

11. A memory system in accordance with claim 9, further comprising:

an isolation circuit coupled to said first and second comparison circuit input lines,

wherein, in response to a control signal, said isolation circuit is rendered conductive to thereby connect said first and second sense nodes to said first and second comparison circuit input lines, respectively.

12. A memory system in accordance with claim 11, wherein said isolation circuit comprises:

a first switching element having a first terminal coupled to said first comparison circuit input line, a second terminal coupled to said first sense node, and a control terminal receiving said control signal; and

a second switching element having a first terminal coupled to said second comparison circuit input line, a second terminal coupled to said second sense node, and a control terminal receiving said control signal,

wherein, upon application of said control signal to said control terminals of said first and second switching elements, said first and second switching elements are rendered conductive to connect said first sense node to said first comparison circuit input line and said second sense node to said second comparisons circuit input line.

15. A memory system in accordance with claim 9, further comprising:

a precharge circuit coupled between said first and second sense nodes of said amplifier circuit,

wherein upon application of a precharge signal to said precharge circuit, said first and second sense nodes are shorted together.

16. A memory system in accordance with claim 1, further comprising a write circuit coupled to said array of programmable resistance elements, said write circuit coupled to supply one of a first potential and a second potential to said array, said first potential and second potentials programming a selected programmable resistance element to said first and second resistance states, respectively.

17. A memory system in accordance with claim 1, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array, said memory system further comprising:

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;

a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows;

a column decoder circuit coupled to select one of said column lines at a time;

a row decoder circuit coupled to select one of said row lines at a time; and

a write circuit coupled to supply one of a first potential and a second potential to said array, said first potential and second potentials programming a programmable resistance element coupled to said selected row and column lines to said first and second resistance states, respectively.

18. A memory system in accordance with claim 16, wherein said first potential is supplied for a first duration to said selected programmable resistance element and said second potential is supplied for a second duration to said selected programmable resistance element.

19. A memory system in accordance with claim 18, wherein said write circuit further comprises:

a first switching element having a first terminal for receiving said first potential, a second terminal coupled to an access node, and a control terminal for receiving a first pulse of said first duration;

a second switching element having a first terminal for receiving said second potential, a second terminal coupled to said access node, and a control terminal for receiving a second pulse of said second duration,

wherein said access node is connected to said array of programmable resistance elements, and said write circuit selectively applies said first and second pulses to said control terminals of said first and second switching elements, respectively, in order to selectively supply said first and second potentials having said first and second durations, respectively, to said array of programmable resistance elements.

20. A memory system in accordance with claim 19, wherein said write circuit further comprises:

a first delay circuit for generating said first pulse; and

a second delay circuit for generating said second pulse.

21. A memory system in accordance with claim 19, wherein said write circuit further comprises:

a first driver circuit having an input node for receiving a first input pulse and an output node for supplying said first pulse to said control terminal of said first switching element, said first pulse having a voltage amplitude greater than said first input pulse; and

a second driver circuit having an input node for receiving a second input pulse and an output node for supplying said second pulse to said control terminal of said second switching element, said second pulse having a voltage amplitude greater than said second input pulse.

22. A memory system in accordance with claim 21, wherein said first driver circuit includes:

a n-channel MOS transistor having a source electrode for connection to a ground potential, a gate electrode for receiving an inverted first input signal, and a drain electrode connected to said output node of said first driver circuit;

a first p-channel MOS transistor having a drain electrode coupled to said gate electrode of said n-channel transistor, a source electrode coupled to a supply potential, and a gate electrode coupled to said output node of said first driver circuit; and

a second p-channel MOS transistor having a drain electrode coupled to a drain electrode of said n-channel MOS transistor, a source electrode coupled to said supply potential, and a gate electrode coupled to said drain electrode of said first p-channel MOS transistor,

wherein a magnitude of said supply potential is greater than said voltage amplitude of said first input pulse.

23. A memory system in accordance with claim 19, wherein said first and second switching elements include MOS transistors.

24. A memory system in accordance with claim 1, wherein each of said programmable resistance elements in said array includes a chalcogenide material.

25. A memory system in accordance with claim 1, wherein each of said programmable resistance elements includes a programmable resistor.

26. A memory system in accordance with claim 25, wherein each of said programmable resistors has a first terminal and a second terminal, said first terminal is coupled to one of said column lines, each said programmable resistance elements further comprising:

a potential barrier device, said potential barrier device coupled between said second terminal of said programmable resistor and one of said row lines.

27. A memory system in accordance with claim 26, wherein said potential barrier device includes a transistor.

28. A memory system in accordance with claim 26, wherein said potential barrier device includes a diode.

29. A memory system in accordance with claim 26, further comprising:

a plurality of biasing circuits respectively coupled to each of said row lines, whereby, when said row lines are in a nonselected state, said plurality of biasing circuits supply a voltage to said nonselected word lines to reverse bias said potential barrier devices to a non-conductive condition.

30. A memory system in accordance with claim 8, further comprising a fixed resistance element coupled to said second comparison circuit input line,

wherein said reference current flows through said fixed resistance element.

31. A memory system in accordance with claim 8, further comprising:

a first shunt protection circuit coupled to said first comparison circuit input line; and

a second shunt protection circuit coupled to said second comparison circuit input line, said first and second shunt protection circuits limiting said sense and reference currents flowing through said first and second comparison circuit inputs lines, respectively.

32. A memory system in accordance with claim 31, wherein said first and second shunt protection circuits each include a diode.

33. A memory system in accordance with claim 31, wherein said first and second shunt protection circuits each include a resistor.

34. A memory system in accordance with claim 31, wherein said first and second shunt protection circuits each include a diode connected in series with a resistor.

85. A memory system in accordance with one of claims 6, 22 or 53, wherein said n-channel transistor is a first n-channel transistor, said memory system further comprising:

a second n-channel transistor connected between said drain of said first p-channel transistor and said gate of said first n-channel transistor.

13. A memory system in accordance with 9, wherein said amplifier circuit includes a cross-coupled latch circuit.

14. A memory system in accordance with claim 13, wherein said cross-coupled latch circuit includes a flip-flop circuit.

35. A semiconductor memory device comprising:

a semiconductor substrate;

a matrix array of memory cells arranged in plural rows and columns on said substrate, each memory cell including a resistor programmable to one of a first resistance state and a second resistance state;

a plurality of column lines respectively coupled to the plural columns of memory cells;

a plurality of row lines respectively coupled to the plural rows of memory cells;

a column decoder circuit connected to select one of said column lines;

a row decoder circuit connected to select one of said row lines;

a column output line coupled to each of said column lines;

a reference line coupled to a fixed resistance element; and

a comparator circuit coupled to said column output line and said reference line, said comparator circuit comparing a sense current flowing through said column output line and a selected programmable resistor coupled to said selected one of said row lines and a reference current flowing through said reference line and said fixed resistance element to thereby output a signal indicative of a resistance state of said programmable resistance element.

36. A semiconductor memory device in accordance with claim 35, wherein each of said programmable resistors includes a chalcogenide material.

37. A semiconductor memory device comprising:

a semiconductor substrate;

an array of programmable resistance elements formed on said substrate, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns;

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns;

a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in each of said rows;

a column decoder circuit connected to select one of said column lines;

a row decoder circuit connected to select one of said row lines;

a column output line coupled to each of said column lines;

a write circuit coupled to said column output line to supply one of a first write voltage and a second write voltage to one of said programmable resistors coupled to said selected column line and said selected row line, said first write voltage programming said programmable resistor to said first resistance state and said second write voltage programming said programmable resistor to said second resistance state.

38. A semiconductor memory device comprising:

an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns;

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns;

a column output line coupled to each of said column lines; and

a shunt protection circuit coupled to limit a current flowing through said column output line and said column lines.

39. A semiconductor memory device in accordance with claim 38, wherein said shunt protection circuit includes a diode.

40. A semiconductor memory device in accordance with claim 38, wherein said shunt protection circuit includes a resistor.

41. A semiconductor memory device in accordance with claim 38, wherein said shunt protection circuit includes a diode connected in series with a resistor.

42. A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in pluralities of rows and columns;

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;

a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows;

a column decoder circuit connected to select one of said column lines; and

a row decoder circuit connected to select one of said row lines, said method comprising the steps of;

driving one of said plurality of column lines to a first potential in accordance with an output of said column decoder;

driving one of said plurality of row lines to a second potential in accordance with an output of said row decoder;

directing a sense current though a programmable resistance element coupled to said one of said plurality of column lines and said one of said plurality of row lines; and

comparing said sense current with a reference current, to determine a programmed resistance of said programmable resistance element.

43. A method of operating a memory in accordance with claim 42, wherein said memory further includes a comparator circuit having first and second nodes, a first comparator input line coupled to each of said plurality of column lines and said comparator circuit, and a second comparator input line coupled to a fixed resistance element and said comparator circuit, said comparing step further comprising the steps of:

precharging said first and second nodes of said comparator circuit to a third potential;

connecting said first and second comparator input lines to said first and second comparator nodes, respectively;

driving said first comparison input line and said first comparison input node to a sense voltage proportional to said sense current; and

driving said second comparison input line and said second comparison input node to a reference voltage proportion to said reference current.

44. A method in accordance with claim 43, further comprising the steps of:

electrically isolating said first comparison input line from said first comparison node and said second comparison input line from said second comparison node;

driving said isolated first comparison node to a fourth voltage higher than said sense voltage and driving said isolated second comparison node to a fifth voltage less than said reference voltage when said sense voltage is higher than said reference voltage;

driving said isolated first comparison node to said fifth voltage, and driving said isolated second comparison node to said fourth voltage when said sense voltage is less than said fifth voltage; and

outputting voltages appearing on said first and second comparison nodes.

45. A method in accordance with claim 42, further comprising the step of limiting a potential appearing on said column lines to not exceed a predetermined value.

46. A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns;

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of;

supplying a current to one of said column lines; and

coupling a shunt circuit to said column lines to limit said current to not exceed a predetermined magnitude.

47. A memory system comprising:

an array of programmable resistance elements, each of which comprising a chalcogenide material and being programmable to one of a first resistance state and a second resistance state; and

a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate readout signals in response to said comparisons.

48. A memory system in accordance with claim 47, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array, said memory system further comprising:

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;

a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows;

a column decoder circuit coupled to select one of said column lines; and

a row decoder circuit coupled to select one of said row lines, thereby selecting one of said programmable resistance elements coupled to said selected column line and said selected row line for coupling with said comparison circuit.

49. A memory system in accordance with claim 48, wherein said column decoder has a plurality of outputs respectively corresponding to said plurality of column lines, one of said plurality of outputs operable to select said selected column line.

50. A memory system in accordance with claim 49, wherein said column decoder circuit further comprises:

a plurality of driver circuits respectively coupled to said plurality of outputs of said column decoder, one of said plurality of driver circuits coupled to said one output and generating a first potential signal operable to select said selected column line, remaining ones of said plurality of driver circuits receiving a second potential signal and supplying, in response thereto, a third potential signal to said remaining outputs of said column decoder, thereby deselecting said column lines other than said selected column line.

51. A memory system in accordance with claim 50, wherein a magnitude of said first potential signal being greater than a magnitude of said second potential signal.

52. A memory system in accordance with claim 50, wherein each of said plurality of driver circuits includes an inverter circuit.

53. A memory system in accordance with claim 50, wherein each of said plurality of driver circuits respectively includes:

a n-channel MOS transistor having a source electrode for connection to a ground potential, a gate electrode for receiving an input signal, and a drain electrode connected to said output node of said first driver circuit;

a first p-channel MOS transistor having a drain electrode coupled to said gate electrode of said n-channel transistor, a source electrode coupled to a supply potential, and a gate electrode coupled to said driver circuit output; and

a second p-channel MOS transistor having a drain electrode coupled to a drain electrode of said n-channel MOS transistor, a source electrode coupled to said supply potential, and a gate electrode coupled to said drain electrode of said first p-channel MOS transistor,

wherein said supply potential is greater than said magnitude of said second potential signal.

54. A memory system in accordance with claim 48, wherein said sense signals include a sense voltage developed by supplying a sense current through said programmable resistance elements and said reference signals include a reference voltage derived from a reference current.

55. A memory system in accordance with claim 54, further comprising:

a first comparison circuit input line coupled to said selected one of said column lines, said sense current flowing through said first comparison circuit input line and through said selected one of said programmable resistance element; and

a second comparison circuit input line for conducting said reference current.

56. A memory system in accordance with claim 55, wherein said comparison circuit comprises:

an amplifier circuit having first and second sense nodes respectively coupled to said first and second comparison input lines, respectively.

57. A memory system in accordance with claim 56, wherein said reference voltage and said sense voltage are generated on said first and second comparison circuit input lines, respectively, and

when said sense voltage is greater than said reference voltage, said amplifier circuit drives said first sense node to a voltage higher than said sense voltage and drives said second sense node to a voltage less than said reference voltage, and

when said sense voltage is less than said reference voltage, said amplifier circuit drives said first sense node to a voltage less than said sense voltage and drives said second sense node to a voltage higher than said reference voltage, said voltages on said first and second sense nodes are supplied to first and second output nodes of said amplifier, respectively.

58. A memory system in accordance with claim 56, further comprising:

an isolation circuit coupled to said first and second comparison circuit input lines,

wherein, in response to a control signal, said isolation circuit is rendered conductive to thereby connect said first and second sense nodes to said first and second comparison circuit input lines, respectively.

59. A memory system in accordance with claim 58, wherein said isolation circuit comprises:

a first switching element having a first terminal coupled to said first comparison circuit input line, a second terminal coupled to said first sense node, and a control terminal receiving said control signal; and

a second switching element having a first terminal coupled to said second comparison circuit input line, a second terminal coupled to said second sense node, and a control terminal receiving said control signal,

wherein, upon application of said control signal to said control terminals of said first and second switching elements, said first and second switching elements are rendered conductive to connect said first sense node to said first comparison circuit input line and said second sense node to said second comparisons circuit input line.

62. A memory system in accordance with claim 56, further comprising:

a precharge circuit coupled between said first and second sense nodes of said amplifier circuit,

wherein upon application of a precharge signal to said precharge circuit, said first and second sense nodes are shorted together.

63. A memory system in accordance with claim 47, further comprising a write circuit coupled to supply one of a first write signal and a second write signal to said array for programming a selected programmable resistance element to said first and second resistance states, respectively.

64. A memory system in accordance with claim 47, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array, said memory system further comprising:

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;

a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows;

a column decoder circuit connected to select one of said column lines at a time;

a row decoder circuit connected to select one of said row lines at a time; and

a write circuit coupled to supply one of first and second write signals to program a selected programmable resistance element coupled to said selected row and column lines to either of said first and second resistance states, respectively.

65. A memory system in accordance with claim 63, wherein said first potential is supplied to said selected programmable resistance element for a first duration, and said second potential is supplied for a second duration to said selected programmable resistance element.

66. A memory system in accordance with claim 65, wherein said write circuit further comprises:

a first switching element having a first terminal for receiving said first potential, a second terminal coupled to an access node, and a control terminal for receiving a first pulse of said first duration;

a second switching element having a first terminal for receiving said second potential, a second terminal coupled to said access node, and a control terminal for receiving a second pulse of said second duration,

wherein said access node is connected to said array of programmable resistance elements, and said write circuit selectively applying said first and second pulses to said control terminals of said first and second switching elements, respectively, to selectively supply said first and second potentials having said first and second durations, respectively, to said array of programmable resistance elements.

67. A memory system in accordance with claim 66, wherein said write circuit further comprises:

a first delay circuit for generating said first pulse; and

a second delay circuit for generating said second pulse.

68. A memory system in accordance with claim 66, wherein said write circuit further comprises:

a first driver circuit having an input node for receiving a first input pulse and an output node for supplying said first pulse to said control terminal of said first switching element, said first pulse having a voltage amplitude greater than said first input pulse; and

a second driver circuit having an input node for receiving a second input pulse and an output node for supplying said second pulse to said control terminal of said second switching element, said second pulse having a voltage amplitude greater than said second input pulse.

69. A memory system in accordance with claim 68, wherein said first driver circuit includes:

a n-channel MOS transistor having a source electrode for connection to a ground potential, a gate electrode for receiving an inverted first input signal, and a drain electrode connected to said output node of said first driver circuit;

a first p-channel MOS transistor having a drain electrode coupled to said gate electrode of said n-channel transistor, a source electrode coupled to a supply potential, and a gate electrode coupled to said output node of said first driver circuit; and

a second p-channel MOS transistor having a drain electrode coupled to a drain electrode of said n-channel MOS transistor, a source electrode coupled to said supply potential, and a gate electrode coupled to said drain electrode of said first p-channel MOS transistor,

wherein a magnitude of said supply potential is greater than said voltage amplitude of said first input pulse.

70. A memory system in accordance with claim 66, wherein said first and second switching elements include MOS transistors.

71. A memory system in accordance with claim 48, wherein each of said programmable resistance elements includes a programmable resistor.

72. A memory system in accordance with claim 71, wherein each of said programmable resistors has a first terminal and a second terminal, said first terminal is coupled to one of said column lines, each said programmable resistance elements further comprising:

a potential barrier device, said potential barrier device coupled between said second terminal of said programmable resistor and one of said row lines.

73. A memory system in accordance with claim 72, wherein said potential barrier device includes a transistor.

74. A memory system in accordance with claim 72, wherein said potential barrier device includes a diode.

75. A memory system in accordance with claim 72, further comprising:

a plurality of biasing circuits respectively coupled to each of said row lines, whereby, when said row lines are in a nonselected state, said plurality of biasing circuits supply a voltage to said nonselected word lines to reverse bias said potential barrier devices to a non-conductive condition.

76. A memory system in accordance with claim 55, further comprising a fixed resistance element coupled to said second comparison circuit input line,

wherein said reference current flows through said fixed resistance element.

77. A memory system in accordance with claim 55, further comprising:

a first shunt protection circuit coupled to said first comparison circuit input line; and

a second shunt protection circuit coupled to said second comparison circuit input line, said first and second shunt protection circuits limiting said sense and reference currents flowing through said first and second comparison circuit inputs lines, respectively.

78. A memory system in accordance with claim 77, wherein said first and second shunt protection circuits each include a diode.

79. A memory system in accordance with claim 77, wherein said first and second shunt protection circuits each include a resistor.

80. A memory system in accordance with claim 77, wherein said first and second shunt protection circuits each include a diode connected in series with a resistor.

86. A memory system in accordance with claim 8 or 55, further comprising:

a first shunt protection circuit coupled to said first comparison circuit input line; and

a second shunt protection circuit coupled to said second comparison circuit input line, said first and second shunt protection circuits limiting voltages appearing on said first and second comparison circuit input lines.

60. A memory system in accordance with 56, wherein said amplifier circuit includes a cross-coupled latch circuit.

61. A memory system in accordance with claim 60, wherein said dross-coupled latch circuit includes a flip-flop circuit.

81. A semiconductor memory device comprising:

an array of programmable resistance elements, each including a resistor comprising chalcogenide material and being programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns;

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns;

a column output line coupled each of said column lines; and

a shunt protection circuit limiting a current flowing through said column output line and said column lines.

82. A semiconductor memory device in accordance with claim 81, wherein said shunt protection circuit includes a diode.

83. A semiconductor memory device in accordance with claim 81, wherein said shunt protection circuit includes a resistor.

84. A semiconductor memory device in accordance with claim 81, wherein said shunt protection circuit includes a diode connected in series with a resistor.

87. A semiconductor memory device comprising:

an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns;

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns;

a column output line coupled to each of said column lines; and

a shunt protection circuit coupled to limit voltages appearing on said column output line and said column lines.

88. A semiconductor memory device in accordance with claim 87, wherein said shunt protection circuit includes a diode.

89. A semiconductor memory device in accordance with claim 87, wherein said shunt protection circuit includes a resistor.

90. A semiconductor memory device in accordance with claim 87, wherein said shunt protection circuit includes a diode connected in series with a resistor.

91. A semiconductor memory device in accordance with claim 87, wherein each said programmable resistors include a chalcogenide material.

92. A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns;

a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of;

supplying a current to one of said column lines; and

coupling a shunt circuit to said column lines to limit a voltage on said one of said column lines to not exceed a predetermined magnitude.