Method and apparatus for reading/writing data in a memory system including programmable resistors
First Claim
1. A memory system comprising:
- an array of programmable resistance elements, each of which being programmable to one of a first resistance state and a second resistance state, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array;
a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate read-out signals in response to said comparisons;
a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;
a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows;
a column decoder circuit coupled to select one of said column lines; and
a row decoder circuit coupled to select one of said row lines, thereby selecting one of said programmable resistance elements coupled to said selected column line and said selected row line.
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Accused Products
Abstract
The present invention relates to circuitry and a related method to reliably write data to an array of programmable resistance elements by selectively applying pulses of a sufficient level to impart either a first (high) or second (low) resistance state to selected programmable resistance elements to store either a binary "1" or "0", respectively. Data is then read from the array by supplying currents though the selected programmable resistance element and a fixed resistive element. A comparison of the resulting voltages on nodes coupled to these resistive elements will indicate whether the resistance value of the programmable resistance element is at a high or low state, i.e., a binary "1" or "0". Further, a shunt circuit is coupled to the selected column lines of the array to protect the programmable resistance elements from excessive spurious or noise currents, which can erroneously program the programmable resistance elements.
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Citations
92 Claims
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1. A memory system comprising:
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an array of programmable resistance elements, each of which being programmable to one of a first resistance state and a second resistance state, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array; a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate read-out signals in response to said comparisons; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows; a column decoder circuit coupled to select one of said column lines; and a row decoder circuit coupled to select one of said row lines, thereby selecting one of said programmable resistance elements coupled to said selected column line and said selected row line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 85)
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- 13. A memory system in accordance with 9, wherein said amplifier circuit includes a cross-coupled latch circuit.
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35. A semiconductor memory device comprising:
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a semiconductor substrate; a matrix array of memory cells arranged in plural rows and columns on said substrate, each memory cell including a resistor programmable to one of a first resistance state and a second resistance state; a plurality of column lines respectively coupled to the plural columns of memory cells; a plurality of row lines respectively coupled to the plural rows of memory cells; a column decoder circuit connected to select one of said column lines; a row decoder circuit connected to select one of said row lines; a column output line coupled to each of said column lines; a reference line coupled to a fixed resistance element; and a comparator circuit coupled to said column output line and said reference line, said comparator circuit comparing a sense current flowing through said column output line and a selected programmable resistor coupled to said selected one of said row lines and a reference current flowing through said reference line and said fixed resistance element to thereby output a signal indicative of a resistance state of said programmable resistance element. - View Dependent Claims (36)
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37. A semiconductor memory device comprising:
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a semiconductor substrate; an array of programmable resistance elements formed on said substrate, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in each of said rows; a column decoder circuit connected to select one of said column lines; a row decoder circuit connected to select one of said row lines; a column output line coupled to each of said column lines; a write circuit coupled to said column output line to supply one of a first write voltage and a second write voltage to one of said programmable resistors coupled to said selected column line and said selected row line, said first write voltage programming said programmable resistor to said first resistance state and said second write voltage programming said programmable resistor to said second resistance state.
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38. A semiconductor memory device comprising:
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an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled to each of said column lines; and a shunt protection circuit coupled to limit a current flowing through said column output line and said column lines. - View Dependent Claims (39, 40, 41)
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42. A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in pluralities of rows and columns;
- a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;
a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows;
a column decoder circuit connected to select one of said column lines; and
a row decoder circuit connected to select one of said row lines, said method comprising the steps of;driving one of said plurality of column lines to a first potential in accordance with an output of said column decoder; driving one of said plurality of row lines to a second potential in accordance with an output of said row decoder; directing a sense current though a programmable resistance element coupled to said one of said plurality of column lines and said one of said plurality of row lines; and comparing said sense current with a reference current, to determine a programmed resistance of said programmable resistance element. - View Dependent Claims (43, 44, 45)
- a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns;
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46. A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns;
- a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of;
supplying a current to one of said column lines; and coupling a shunt circuit to said column lines to limit said current to not exceed a predetermined magnitude.
- a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of;
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47. A memory system comprising:
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an array of programmable resistance elements, each of which comprising a chalcogenide material and being programmable to one of a first resistance state and a second resistance state; and a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate readout signals in response to said comparisons. - View Dependent Claims (48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 86)
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- 60. A memory system in accordance with 56, wherein said amplifier circuit includes a cross-coupled latch circuit.
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81. A semiconductor memory device comprising:
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an array of programmable resistance elements, each including a resistor comprising chalcogenide material and being programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled each of said column lines; and a shunt protection circuit limiting a current flowing through said column output line and said column lines. - View Dependent Claims (82, 83, 84)
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87. A semiconductor memory device comprising:
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an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled to each of said column lines; and a shunt protection circuit coupled to limit voltages appearing on said column output line and said column lines. - View Dependent Claims (88, 89, 90, 91)
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92. A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns;
- a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of;
supplying a current to one of said column lines; and coupling a shunt circuit to said column lines to limit a voltage on said one of said column lines to not exceed a predetermined magnitude.
- a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of;
Specification